985 	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);  in vgpu_mm_switch()
986 	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));  in vgpu_mm_switch()
1029 	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);  in gen6_mm_switch()
1030 	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));  in gen6_mm_switch()
1044 		I915_WRITE(RING_MODE_GEN7(ring),  in gen8_ppgtt_enable()
1057 	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);  in gen7_ppgtt_enable()
1066 	I915_WRITE(GAM_ECOCHK, ecochk);  in gen7_ppgtt_enable()
1070 		I915_WRITE(RING_MODE_GEN7(ring),  in gen7_ppgtt_enable()
1081 	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |  in gen6_ppgtt_enable()
1085 	I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);  in gen6_ppgtt_enable()
1088 	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);  in gen6_ppgtt_enable()
1090 	I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));  in gen6_ppgtt_enable()
1619 			I915_WRITE(RING_FAULT_REG(ring),  in i915_check_and_clear_faults()
1631 		I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);  in i915_ggtt_flush()
1776 	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);  in gen8_ggtt_insert_entries()
1820 	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);  in gen6_ggtt_insert_entries()
2306 	I915_WRITE(GEN8_PRIVATE_PAT, pat);  in bdw_setup_private_ppat()
2307 	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);  in bdw_setup_private_ppat()
2341 	I915_WRITE(GEN8_PRIVATE_PAT, pat);  in chv_setup_private_ppat()
2342 	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);  in chv_setup_private_ppat()