79 	tmp = I915_READ(crt->adpa_reg);  in intel_crt_get_hw_state()
98 	tmp = I915_READ(crt->adpa_reg);  in intel_crt_get_flags()
146 	WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n");  in hsw_crt_pre_enable()
218 	val = I915_READ(SPLL_CTL);  in hsw_crt_post_disable()
348 		save_adpa = adpa = I915_READ(crt->adpa_reg);  in intel_ironlake_crt_detect_hotplug()
357 		if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,  in intel_ironlake_crt_detect_hotplug()
368 	adpa = I915_READ(crt->adpa_reg);  in intel_ironlake_crt_detect_hotplug()
387 	save_adpa = adpa = I915_READ(crt->adpa_reg);  in valleyview_crt_detect_hotplug()
394 	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,  in valleyview_crt_detect_hotplug()
401 	adpa = I915_READ(crt->adpa_reg);  in valleyview_crt_detect_hotplug()
443 	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);  in intel_crt_detect_hotplug()
450 		if (wait_for((I915_READ(PORT_HOTPLUG_EN) &  in intel_crt_detect_hotplug()
456 	stat = I915_READ(PORT_HOTPLUG_STAT);  in intel_crt_detect_hotplug()
568 	save_bclrpat = I915_READ(bclrpat_reg);  in intel_crt_load_detect()
569 	save_vtotal = I915_READ(vtotal_reg);  in intel_crt_load_detect()
570 	vblank = I915_READ(vblank_reg);  in intel_crt_load_detect()
582 		uint32_t pipeconf = I915_READ(pipeconf_reg);  in intel_crt_load_detect()
603 			uint32_t vsync = I915_READ(vsync_reg);  in intel_crt_load_detect()
621 		while (I915_READ(pipe_dsl_reg) >= vactive)  in intel_crt_load_detect()
623 		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)  in intel_crt_load_detect()
636 		} while ((I915_READ(pipe_dsl_reg) == dsl));  in intel_crt_load_detect()
781 		adpa = I915_READ(crt->adpa_reg);  in intel_crt_reset()
934 		dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;  in intel_crt_init()