1151 	uint32_t ctrl1, cfgcr1, cfgcr2;  in skl_ddi_pll_select()  local
1171 		cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |  in skl_ddi_pll_select()
1192 		cfgcr1 = cfgcr2 = 0;  in skl_ddi_pll_select()
1198 	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;  in skl_ddi_pll_select()
1852 	u32 ctl, cfgcr1, cfgcr2;  member
1861 		.cfgcr2 = DPLL1_CFGCR2,
1867 		.cfgcr2 = DPLL2_CFGCR2,
1873 		.cfgcr2 = DPLL3_CFGCR2,
1897 	I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);  in skl_ddi_pll_enable()
1899 	POSTING_READ(regs[pll->id].cfgcr2);  in skl_ddi_pll_enable()
1944 		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);  in skl_ddi_pll_get_hw_state()