712 			       uint32_t dpll)  in skl_calc_wrpll_link()  argument
718 	cfgcr1_reg = GET_CFG_CR1_REG(dpll);  in skl_calc_wrpll_link()
719 	cfgcr2_reg = GET_CFG_CR2_REG(dpll);  in skl_calc_wrpll_link()
777 	uint32_t dpll_ctl1, dpll;  in skl_ddi_clock_get()  local
779 	dpll = pipe_config->ddi_pll_sel;  in skl_ddi_clock_get()
783 	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {  in skl_ddi_clock_get()
784 		link_clock = skl_calc_wrpll_link(dev_priv, dpll);  in skl_ddi_clock_get()
786 		link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);  in skl_ddi_clock_get()
787 		link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);  in skl_ddi_clock_get()
1537 		uint32_t dpll = crtc->config->ddi_pll_sel;  in intel_ddi_pre_enable()  local
1545 			WARN_ON(dpll != SKL_DPLL0);  in intel_ddi_pre_enable()
1549 			val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |  in intel_ddi_pre_enable()
1550 				 DPLL_CTRL1_SSC(dpll) |  in intel_ddi_pre_enable()
1551 				 DPLL_CRTL1_LINK_RATE_MASK(dpll));  in intel_ddi_pre_enable()
1552 			val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);  in intel_ddi_pre_enable()
1563 		val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |  in intel_ddi_pre_enable()
1881 	unsigned int dpll;  in skl_ddi_pll_enable()  local
1885 	dpll = pll->id + 1;  in skl_ddi_pll_enable()
1889 	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |  in skl_ddi_pll_enable()
1890 		 DPLL_CRTL1_LINK_RATE_MASK(dpll));  in skl_ddi_pll_enable()
1891 	val |= pll->config.hw_state.ctrl1 << (dpll * 6);  in skl_ddi_pll_enable()
1905 	if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))  in skl_ddi_pll_enable()
1906 		DRM_ERROR("DPLL %d not locked\n", dpll);  in skl_ddi_pll_enable()
1925 	unsigned int dpll;  in skl_ddi_pll_get_hw_state()  local
1932 	dpll = pll->id + 1;  in skl_ddi_pll_get_hw_state()
1939 	hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;  in skl_ddi_pll_get_hw_state()
1942 	if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {  in skl_ddi_pll_get_hw_state()