830 	u32 val, pll;  in hsw_ddi_clock_get()  local
850 		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;  in hsw_ddi_clock_get()
851 		if (pll == SPLL_PLL_FREQ_810MHz)  in hsw_ddi_clock_get()
853 		else if (pll == SPLL_PLL_FREQ_1350MHz)  in hsw_ddi_clock_get()
855 		else if (pll == SPLL_PLL_FREQ_2700MHz)  in hsw_ddi_clock_get()
964 		struct intel_shared_dpll *pll;  in hsw_ddi_pll_select()  local
976 		pll = intel_get_shared_dpll(intel_crtc, crtc_state);  in hsw_ddi_pll_select()
977 		if (pll == NULL) {  in hsw_ddi_pll_select()
983 		crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);  in hsw_ddi_pll_select()
1150 	struct intel_shared_dpll *pll;  in skl_ddi_pll_select()  local
1200 	pll = intel_get_shared_dpll(intel_crtc, crtc_state);  in skl_ddi_pll_select()
1201 	if (pll == NULL) {  in skl_ddi_pll_select()
1208 	crtc_state->ddi_pll_sel = pll->id + 1;  in skl_ddi_pll_select()
1792 			       struct intel_shared_dpll *pll)  in hsw_ddi_pll_enable()  argument
1794 	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);  in hsw_ddi_pll_enable()
1795 	POSTING_READ(WRPLL_CTL(pll->id));  in hsw_ddi_pll_enable()
1800 				struct intel_shared_dpll *pll)  in hsw_ddi_pll_disable()  argument
1804 	val = I915_READ(WRPLL_CTL(pll->id));  in hsw_ddi_pll_disable()
1805 	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);  in hsw_ddi_pll_disable()
1806 	POSTING_READ(WRPLL_CTL(pll->id));  in hsw_ddi_pll_disable()
1810 				     struct intel_shared_dpll *pll,  in hsw_ddi_pll_get_hw_state()  argument
1818 	val = I915_READ(WRPLL_CTL(pll->id));  in hsw_ddi_pll_get_hw_state()
1878 			       struct intel_shared_dpll *pll)  in skl_ddi_pll_enable()  argument
1885 	dpll = pll->id + 1;  in skl_ddi_pll_enable()
1891 	val |= pll->config.hw_state.ctrl1 << (dpll * 6);  in skl_ddi_pll_enable()
1896 	I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);  in skl_ddi_pll_enable()
1897 	I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);  in skl_ddi_pll_enable()
1898 	POSTING_READ(regs[pll->id].cfgcr1);  in skl_ddi_pll_enable()
1899 	POSTING_READ(regs[pll->id].cfgcr2);  in skl_ddi_pll_enable()
1902 	I915_WRITE(regs[pll->id].ctl,  in skl_ddi_pll_enable()
1903 		   I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);  in skl_ddi_pll_enable()
1910 				struct intel_shared_dpll *pll)  in skl_ddi_pll_disable()  argument
1915 	I915_WRITE(regs[pll->id].ctl,  in skl_ddi_pll_disable()
1916 		   I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);  in skl_ddi_pll_disable()
1917 	POSTING_READ(regs[pll->id].ctl);  in skl_ddi_pll_disable()
1921 				     struct intel_shared_dpll *pll,  in skl_ddi_pll_get_hw_state()  argument
1932 	dpll = pll->id + 1;  in skl_ddi_pll_get_hw_state()
1934 	val = I915_READ(regs[pll->id].ctl);  in skl_ddi_pll_get_hw_state()
1943 		hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);  in skl_ddi_pll_get_hw_state()
1944 		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);  in skl_ddi_pll_get_hw_state()