Lines Matching refs:DSPCNTR
1327 reg = DSPCNTR(plane); in assert_plane()
1348 reg = DSPCNTR(pipe); in assert_planes_disabled()
1358 reg = DSPCNTR(i); in assert_planes_disabled()
2676 u32 reg = DSPCNTR(plane); in i9xx_update_primary_plane()
2805 u32 reg = DSPCNTR(plane); in ironlake_update_primary_plane()
6952 val = I915_READ(DSPCNTR(plane)); in i9xx_get_initial_plane_config()
8113 val = I915_READ(DSPCNTR(pipe)); in ironlake_get_initial_plane_config()
9955 reg = DSPCNTR(intel_crtc->plane); in ilk_do_mmio_flip()
13921 reg = DSPCNTR(!crtc->plane); in intel_check_plane_mapping()
14127 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; in primary_get_hw_state()
14515 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()