Lines Matching refs:I915_READ
137 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; in intel_pch_rawclk()
145 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; in intel_fdi_link_freq()
998 line1 = I915_READ(reg) & line_mask; in pipe_dsl_stopped()
1000 line2 = I915_READ(reg) & line_mask; in pipe_dsl_stopped()
1032 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, in intel_wait_for_pipe_off()
1084 return I915_READ(SDEISR) & bit; in ibx_digital_port_connected()
1101 val = I915_READ(reg); in assert_pll()
1167 val = I915_READ(reg); in assert_fdi_tx()
1171 val = I915_READ(reg); in assert_fdi_tx()
1189 val = I915_READ(reg); in assert_fdi_rx()
1213 val = I915_READ(reg); in assert_fdi_tx_pll_enabled()
1225 val = I915_READ(reg); in assert_fdi_rx_pll()
1248 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
1251 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) in assert_panel_unlocked()
1260 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) in assert_panel_unlocked()
1264 val = I915_READ(pp_reg); in assert_panel_unlocked()
1281 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; in assert_cursor()
1283 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; in assert_cursor()
1311 val = I915_READ(reg); in assert_pipe()
1328 val = I915_READ(reg); in assert_plane()
1349 val = I915_READ(reg); in assert_planes_disabled()
1359 val = I915_READ(reg); in assert_planes_disabled()
1377 val = I915_READ(PLANE_CTL(pipe, sprite)); in assert_sprites_disabled()
1385 val = I915_READ(reg); in assert_sprites_disabled()
1392 val = I915_READ(reg); in assert_sprites_disabled()
1398 val = I915_READ(reg); in assert_sprites_disabled()
1418 val = I915_READ(PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
1432 val = I915_READ(reg); in assert_pch_transcoder_disabled()
1447 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); in dp_pipe_enabled()
1513 u32 val = I915_READ(reg); in assert_pch_dp_disabled()
1526 u32 val = I915_READ(reg); in assert_pch_hdmi_disabled()
1547 val = I915_READ(reg); in assert_pch_ports_disabled()
1553 val = I915_READ(reg); in assert_pch_ports_disabled()
1604 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in vlv_enable_pll()
1651 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in chv_enable_pll()
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1752 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1754 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1846 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) in vlv_wait_port_ready()
1848 port_name(dport->port), I915_READ(dpll_reg)); in vlv_wait_port_ready()
1966 val = I915_READ(reg); in ironlake_enable_pch_transcoder()
1972 val = I915_READ(reg); in ironlake_enable_pch_transcoder()
1973 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()
1995 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) in ironlake_enable_pch_transcoder()
2012 val = I915_READ(_TRANSA_CHICKEN2); in lpt_enable_pch_transcoder()
2017 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
2026 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) in lpt_enable_pch_transcoder()
2044 val = I915_READ(reg); in ironlake_disable_pch_transcoder()
2048 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) in ironlake_disable_pch_transcoder()
2054 val = I915_READ(reg); in ironlake_disable_pch_transcoder()
2064 val = I915_READ(LPT_TRANSCONF); in lpt_disable_pch_transcoder()
2068 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) in lpt_disable_pch_transcoder()
2072 val = I915_READ(_TRANSA_CHICKEN2); in lpt_disable_pch_transcoder()
2125 val = I915_READ(reg); in intel_enable_pipe()
2163 val = I915_READ(reg); in intel_disable_pipe()
2194 I915_WRITE(reg, I915_READ(reg)); in intel_flush_primary_plane()
3247 temp = I915_READ(reg); in intel_fdi_normal_train()
3258 temp = I915_READ(reg); in intel_fdi_normal_train()
3274 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | in intel_fdi_normal_train()
3293 temp = I915_READ(reg); in ironlake_fdi_link_train()
3297 I915_READ(reg); in ironlake_fdi_link_train()
3302 temp = I915_READ(reg); in ironlake_fdi_link_train()
3310 temp = I915_READ(reg); in ironlake_fdi_link_train()
3325 temp = I915_READ(reg); in ironlake_fdi_link_train()
3339 temp = I915_READ(reg); in ironlake_fdi_link_train()
3345 temp = I915_READ(reg); in ironlake_fdi_link_train()
3355 temp = I915_READ(reg); in ironlake_fdi_link_train()
3390 temp = I915_READ(reg); in gen6_fdi_link_train()
3400 temp = I915_READ(reg); in gen6_fdi_link_train()
3414 temp = I915_READ(reg); in gen6_fdi_link_train()
3429 temp = I915_READ(reg); in gen6_fdi_link_train()
3439 temp = I915_READ(reg); in gen6_fdi_link_train()
3456 temp = I915_READ(reg); in gen6_fdi_link_train()
3467 temp = I915_READ(reg); in gen6_fdi_link_train()
3482 temp = I915_READ(reg); in gen6_fdi_link_train()
3492 temp = I915_READ(reg); in gen6_fdi_link_train()
3522 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3531 I915_READ(FDI_RX_IIR(pipe))); in ivb_manual_fdi_link_train()
3537 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3543 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3551 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3564 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3574 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3578 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { in ivb_manual_fdi_link_train()
3593 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3599 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3609 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
3613 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { in ivb_manual_fdi_link_train()
3639 temp = I915_READ(reg); in ironlake_fdi_pll_enable()
3642 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
3649 temp = I915_READ(reg); in ironlake_fdi_pll_enable()
3657 temp = I915_READ(reg); in ironlake_fdi_pll_enable()
3675 temp = I915_READ(reg); in ironlake_fdi_pll_disable()
3680 temp = I915_READ(reg); in ironlake_fdi_pll_disable()
3687 temp = I915_READ(reg); in ironlake_fdi_pll_disable()
3705 temp = I915_READ(reg); in ironlake_fdi_disable()
3710 temp = I915_READ(reg); in ironlake_fdi_disable()
3712 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
3724 temp = I915_READ(reg); in ironlake_fdi_disable()
3730 temp = I915_READ(reg); in ironlake_fdi_disable()
3740 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
3917 I915_READ(HTOTAL(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
3919 I915_READ(HBLANK(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
3921 I915_READ(HSYNC(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
3924 I915_READ(VTOTAL(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
3926 I915_READ(VBLANK(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
3928 I915_READ(VSYNC(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
3930 I915_READ(VSYNCSHIFT(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
3938 temp = I915_READ(SOUTH_CHICKEN1); in cpt_set_fdi_bc_bifurcation()
3942 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
3943 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
4001 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); in ironlake_pch_enable()
4011 temp = I915_READ(PCH_DPLL_SEL); in ironlake_pch_enable()
4038 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
4040 temp = I915_READ(reg); in ironlake_pch_enable()
4248 temp = I915_READ(dslreg); in cpt_verify_modeset()
4250 if (wait_for(I915_READ(dslreg) != temp, 5)) { in cpt_verify_modeset()
4251 if (wait_for(I915_READ(dslreg) != temp, 5)) in cpt_verify_modeset()
4383 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) in hsw_disable_ips()
4424 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == in intel_crtc_load_lut()
4775 temp = I915_READ(reg); in ironlake_crtc_disable()
4782 temp = I915_READ(PCH_DPLL_SEL); in ironlake_crtc_disable()
4879 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); in i9xx_pfit_enable()
5230 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
5420 I915_READ(PFIT_CONTROL)); in i9xx_pfit_disable()
6647 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); in intel_set_pipe_timings()
6665 tmp = I915_READ(HTOTAL(cpu_transcoder)); in intel_get_pipe_timings()
6668 tmp = I915_READ(HBLANK(cpu_transcoder)); in intel_get_pipe_timings()
6671 tmp = I915_READ(HSYNC(cpu_transcoder)); in intel_get_pipe_timings()
6675 tmp = I915_READ(VTOTAL(cpu_transcoder)); in intel_get_pipe_timings()
6678 tmp = I915_READ(VBLANK(cpu_transcoder)); in intel_get_pipe_timings()
6681 tmp = I915_READ(VSYNC(cpu_transcoder)); in intel_get_pipe_timings()
6685 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { in intel_get_pipe_timings()
6691 tmp = I915_READ(PIPESRC(crtc->pipe)); in intel_get_pipe_timings()
6728 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
6889 tmp = I915_READ(PFIT_CONTROL); in i9xx_get_pfit_config()
6903 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); in i9xx_get_pfit_config()
6906 I915_READ(LVDS) & LVDS_BORDER_ENABLE; in i9xx_get_pfit_config()
6952 val = I915_READ(DSPCNTR(plane)); in i9xx_get_initial_plane_config()
6978 offset = I915_READ(DSPTILEOFF(plane)); in i9xx_get_initial_plane_config()
6980 offset = I915_READ(DSPLINOFF(plane)); in i9xx_get_initial_plane_config()
6981 base = I915_READ(DSPSURF(plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
6983 base = I915_READ(DSPADDR(plane)); in i9xx_get_initial_plane_config()
6987 val = I915_READ(PIPESRC(pipe)); in i9xx_get_initial_plane_config()
6991 val = I915_READ(DSPSTRIDE(pipe)); in i9xx_get_initial_plane_config()
7052 tmp = I915_READ(PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
7083 tmp = I915_READ(DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
7089 tmp = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7099 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7109 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
7110 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
7172 val = I915_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()
7280 tmp = I915_READ(SOUTH_CHICKEN2); in lpt_reset_fdi_mphy()
7284 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & in lpt_reset_fdi_mphy()
7288 tmp = I915_READ(SOUTH_CHICKEN2); in lpt_reset_fdi_mphy()
7292 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & in lpt_reset_fdi_mphy()
7907 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); in intel_pch_transcoder_get_m_n()
7908 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); in intel_pch_transcoder_get_m_n()
7909 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
7911 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); in intel_pch_transcoder_get_m_n()
7912 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
7926 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); in intel_cpu_transcoder_get_m_n()
7927 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); in intel_cpu_transcoder_get_m_n()
7928 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) in intel_cpu_transcoder_get_m_n()
7930 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); in intel_cpu_transcoder_get_m_n()
7931 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) in intel_cpu_transcoder_get_m_n()
7939 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); in intel_cpu_transcoder_get_m_n()
7940 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); in intel_cpu_transcoder_get_m_n()
7941 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) in intel_cpu_transcoder_get_m_n()
7943 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); in intel_cpu_transcoder_get_m_n()
7944 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) in intel_cpu_transcoder_get_m_n()
7948 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
7949 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
7950 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
7952 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
7953 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
7983 tmp = I915_READ(PS_CTL(crtc->pipe)); in skylake_get_pfit_config()
7987 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); in skylake_get_pfit_config()
7988 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); in skylake_get_pfit_config()
8013 val = I915_READ(PLANE_CTL(pipe, 0)); in skylake_get_initial_plane_config()
8044 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; in skylake_get_initial_plane_config()
8047 offset = I915_READ(PLANE_OFFSET(pipe, 0)); in skylake_get_initial_plane_config()
8049 val = I915_READ(PLANE_SIZE(pipe, 0)); in skylake_get_initial_plane_config()
8053 val = I915_READ(PLANE_STRIDE(pipe, 0)); in skylake_get_initial_plane_config()
8083 tmp = I915_READ(PF_CTL(crtc->pipe)); in ironlake_get_pfit_config()
8087 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
8088 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
8113 val = I915_READ(DSPCNTR(pipe)); in ironlake_get_initial_plane_config()
8137 base = I915_READ(DSPSURF(pipe)) & 0xfffff000; in ironlake_get_initial_plane_config()
8139 offset = I915_READ(DSPOFFSET(pipe)); in ironlake_get_initial_plane_config()
8142 offset = I915_READ(DSPTILEOFF(pipe)); in ironlake_get_initial_plane_config()
8144 offset = I915_READ(DSPLINOFF(pipe)); in ironlake_get_initial_plane_config()
8148 val = I915_READ(PIPESRC(pipe)); in ironlake_get_initial_plane_config()
8152 val = I915_READ(DSPSTRIDE(pipe)); in ironlake_get_initial_plane_config()
8183 tmp = I915_READ(PIPECONF(crtc->pipe)); in ironlake_get_pipe_config()
8207 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { in ironlake_get_pipe_config()
8212 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); in ironlake_get_pipe_config()
8222 tmp = I915_READ(PCH_DPLL_SEL); in ironlake_get_pipe_config()
8260 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); in assert_can_disable_lcpll()
8261 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); in assert_can_disable_lcpll()
8262 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); in assert_can_disable_lcpll()
8263 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); in assert_can_disable_lcpll()
8264 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); in assert_can_disable_lcpll()
8265 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
8268 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
8270 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, in assert_can_disable_lcpll()
8272 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, in assert_can_disable_lcpll()
8274 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); in assert_can_disable_lcpll()
8290 return I915_READ(D_COMP_HSW); in hsw_read_dcomp()
8292 return I915_READ(D_COMP_BDW); in hsw_read_dcomp()
8326 val = I915_READ(LCPLL_CTL); in hsw_disable_lcpll()
8332 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & in hsw_disable_lcpll()
8336 val = I915_READ(LCPLL_CTL); in hsw_disable_lcpll()
8343 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) in hsw_disable_lcpll()
8356 val = I915_READ(LCPLL_CTL); in hsw_disable_lcpll()
8371 val = I915_READ(LCPLL_CTL); in hsw_restore_lcpll()
8394 val = I915_READ(LCPLL_CTL); in hsw_restore_lcpll()
8398 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) in hsw_restore_lcpll()
8402 val = I915_READ(LCPLL_CTL); in hsw_restore_lcpll()
8406 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & in hsw_restore_lcpll()
8445 val = I915_READ(SOUTH_DSPCLK_GATE_D); in hsw_enable_pc8()
8465 val = I915_READ(SOUTH_DSPCLK_GATE_D); in hsw_disable_pc8()
8490 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); in skylake_get_ddi_pll()
8500 dpll_ctl1 = I915_READ(DPLL_CTRL1); in skylake_get_ddi_pll()
8519 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); in haswell_get_ddi_pll()
8540 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); in haswell_get_ddi_port_state()
8562 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { in haswell_get_ddi_port_state()
8565 tmp = I915_READ(FDI_RX_CTL(PIPE_A)); in haswell_get_ddi_port_state()
8588 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); in haswell_get_pipe_config()
8614 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); in haswell_get_pipe_config()
8632 (I915_READ(IPS_CTL) & IPS_ENABLE); in haswell_get_pipe_config()
8636 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; in haswell_get_pipe_config()
9273 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); in i9xx_crtc_clock_get()
9355 int htot = I915_READ(HTOTAL(cpu_transcoder)); in intel_crtc_mode_get()
9356 int hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_crtc_mode_get()
9357 int vtot = I915_READ(VTOTAL(cpu_transcoder)); in intel_crtc_mode_get()
9358 int vsync = I915_READ(VSYNC(cpu_transcoder)); in intel_crtc_mode_get()
9374 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); in intel_crtc_mode_get()
9375 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); in intel_crtc_mode_get()
9376 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); in intel_crtc_mode_get()
9419 dpll = I915_READ(dpll_reg); in intel_decrease_pllclock()
9423 dpll = I915_READ(dpll_reg); in intel_decrease_pllclock()
9610 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == in page_flip_finished()
9612 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), in page_flip_finished()
9745 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen4_queue_flip()
9781 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen6_queue_flip()
9921 ctl = I915_READ(PLANE_CTL(pipe, 0)); in skl_do_mmio_flip()
9956 dspcntr = I915_READ(reg); in ilk_do_mmio_flip()
10070 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); in __intel_pageflip_stall_check()
10072 addr = I915_READ(DSPADDR(intel_crtc->plane)); in __intel_pageflip_stall_check()
10196 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; in intel_crtc_page_flip()
12249 val = I915_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_get_hw_state()
12251 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); in ibx_pch_dpll_get_hw_state()
12252 hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); in ibx_pch_dpll_get_hw_state()
13016 if ((I915_READ(DP_A) & DP_DETECTED) == 0) in has_edp_a()
13019 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) in has_edp_a()
13063 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; in intel_setup_outputs()
13071 found = I915_READ(SFUSE_STRAP); in intel_setup_outputs()
13086 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { in intel_setup_outputs()
13091 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) in intel_setup_outputs()
13095 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) in intel_setup_outputs()
13098 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) in intel_setup_outputs()
13101 if (I915_READ(PCH_DP_C) & DP_DETECTED) in intel_setup_outputs()
13104 if (I915_READ(PCH_DP_D) & DP_DETECTED) in intel_setup_outputs()
13116 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && in intel_setup_outputs()
13120 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || in intel_setup_outputs()
13124 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && in intel_setup_outputs()
13128 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || in intel_setup_outputs()
13133 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) in intel_setup_outputs()
13137 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) in intel_setup_outputs()
13145 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { in intel_setup_outputs()
13159 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { in intel_setup_outputs()
13164 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { in intel_setup_outputs()
13175 (I915_READ(DP_D) & DP_DETECTED)) in intel_setup_outputs()
13797 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & in intel_modeset_init()
13922 val = I915_READ(reg); in intel_check_plane_mapping()
13939 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); in intel_sanitize_crtc()
14097 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { in i915_redisable_vga_power_on()
14127 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; in primary_get_hw_state()
14502 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); in intel_display_capture_error_state()
14511 error->cursor[i].control = I915_READ(CURCNTR(i)); in intel_display_capture_error_state()
14512 error->cursor[i].position = I915_READ(CURPOS(i)); in intel_display_capture_error_state()
14513 error->cursor[i].base = I915_READ(CURBASE(i)); in intel_display_capture_error_state()
14515 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()
14516 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); in intel_display_capture_error_state()
14518 error->plane[i].size = I915_READ(DSPSIZE(i)); in intel_display_capture_error_state()
14519 error->plane[i].pos = I915_READ(DSPPOS(i)); in intel_display_capture_error_state()
14522 error->plane[i].addr = I915_READ(DSPADDR(i)); in intel_display_capture_error_state()
14524 error->plane[i].surface = I915_READ(DSPSURF(i)); in intel_display_capture_error_state()
14525 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); in intel_display_capture_error_state()
14528 error->pipe[i].source = I915_READ(PIPESRC(i)); in intel_display_capture_error_state()
14531 error->pipe[i].stat = I915_READ(PIPESTAT(i)); in intel_display_capture_error_state()
14549 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); in intel_display_capture_error_state()
14550 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); in intel_display_capture_error_state()
14551 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); in intel_display_capture_error_state()
14552 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_display_capture_error_state()
14553 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); in intel_display_capture_error_state()
14554 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); in intel_display_capture_error_state()
14555 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); in intel_display_capture_error_state()