1252 			panel_pipe = PIPE_B;  in assert_panel_unlocked()
1261 			panel_pipe = PIPE_B;  in assert_panel_unlocked()
1303 	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in assert_pipe()
1751 		I915_WRITE(DPLL(PIPE_B),  in i9xx_disable_pll()
1752 			   I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);  in i9xx_disable_pll()
1759 	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in i9xx_disable_pll()
1780 	if (pipe == PIPE_B)  in vlv_disable_pll()
1810 	if (pipe != PIPE_B) {  in chv_disable_pll()
2128 			  (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));  in intel_enable_pipe()
2176 	    !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in intel_disable_pipe()
2700 		if (intel_crtc->pipe == PIPE_B)  in i9xx_update_primary_plane()
3942 	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);  in cpt_set_fdi_bc_bifurcation()
3961 	case PIPE_B:  in ivybridge_update_fdi_bc_bifurcation()
5291 	if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {  in valleyview_crtc_enable()
5736 	case PIPE_B:  in ironlake_check_fdi_lanes()
5750 		if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {  in ironlake_check_fdi_lanes()
6206 	if (crtc->pipe == PIPE_B)  in vlv_update_pll()
6237 	if (pipe == PIPE_B)  in vlv_prepare_pll()
6646 	    (pipe == PIPE_B || pipe == PIPE_C))  in intel_set_pipe_timings()
6727 	    (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in i9xx_set_pipeconf()
6895 		if (crtc->pipe != PIPE_B)  in i9xx_get_pfit_config()
8599 			trans_edp_pipe = PIPE_B;  in haswell_get_pipe_config()
11295 		    (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))  in check_crtc_state()