Lines Matching refs:crtc
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
98 static void haswell_set_pipeconf(struct drm_crtc *crtc);
99 static void intel_set_pipe_csc(struct drm_crtc *crtc);
100 static void vlv_prepare_pll(struct intel_crtc *crtc,
102 static void chv_prepare_pll(struct intel_crtc *crtc,
104 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
416 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) in intel_pipe_has_type() argument
418 struct drm_device *dev = crtc->base.dev; in intel_pipe_has_type()
421 for_each_encoder_on_crtc(dev, &crtc->base, encoder) in intel_pipe_has_type()
447 if (connector_state->crtc != crtc_state->base.crtc) in intel_pipe_will_have_type()
465 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_ironlake_limit()
489 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_g4x_limit()
511 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_limit()
627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in i9xx_find_best_dpll() local
628 struct drm_device *dev = crtc->base.dev; in i9xx_find_best_dpll()
690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in pnv_find_best_dpll() local
691 struct drm_device *dev = crtc->base.dev; in pnv_find_best_dpll()
751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in g4x_find_best_dpll() local
752 struct drm_device *dev = crtc->base.dev; in g4x_find_best_dpll()
850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in vlv_find_best_dpll() local
851 struct drm_device *dev = crtc->base.dev; in vlv_find_best_dpll()
904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in chv_find_best_dpll() local
905 struct drm_device *dev = crtc->base.dev; in chv_find_best_dpll()
956 bool intel_crtc_active(struct drm_crtc *crtc) in intel_crtc_active() argument
958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_active()
973 return intel_crtc->active && crtc->primary->state->fb && in intel_crtc_active()
980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_pipe_to_cpu_transcoder() local
981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_pipe_to_cpu_transcoder()
1021 static void intel_wait_for_pipe_off(struct intel_crtc *crtc) in intel_wait_for_pipe_off() argument
1023 struct drm_device *dev = crtc->base.dev; in intel_wait_for_pipe_off()
1025 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; in intel_wait_for_pipe_off()
1026 enum pipe pipe = crtc->pipe; in intel_wait_for_pipe_off()
1127 intel_crtc_to_shared_dpll(struct intel_crtc *crtc) in intel_crtc_to_shared_dpll() argument
1129 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_crtc_to_shared_dpll()
1131 if (crtc->config->shared_dpll < 0) in intel_crtc_to_shared_dpll()
1134 return &dev_priv->shared_dplls[crtc->config->shared_dpll]; in intel_crtc_to_shared_dpll()
1405 static void assert_vblank_disabled(struct drm_crtc *crtc) in assert_vblank_disabled() argument
1407 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) in assert_vblank_disabled()
1408 drm_crtc_vblank_put(crtc); in assert_vblank_disabled()
1583 static void vlv_enable_pll(struct intel_crtc *crtc, in vlv_enable_pll() argument
1586 struct drm_device *dev = crtc->base.dev; in vlv_enable_pll()
1588 int reg = DPLL(crtc->pipe); in vlv_enable_pll()
1591 assert_pipe_disabled(dev_priv, crtc->pipe); in vlv_enable_pll()
1598 assert_panel_unlocked(dev_priv, crtc->pipe); in vlv_enable_pll()
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); in vlv_enable_pll()
1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1608 POSTING_READ(DPLL_MD(crtc->pipe)); in vlv_enable_pll()
1622 static void chv_enable_pll(struct intel_crtc *crtc, in chv_enable_pll() argument
1625 struct drm_device *dev = crtc->base.dev; in chv_enable_pll()
1627 int pipe = crtc->pipe; in chv_enable_pll()
1631 assert_pipe_disabled(dev_priv, crtc->pipe); in chv_enable_pll()
1663 struct intel_crtc *crtc; in intel_num_dvo_pipes() local
1666 for_each_intel_crtc(dev, crtc) in intel_num_dvo_pipes()
1667 count += crtc->active && in intel_num_dvo_pipes()
1668 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); in intel_num_dvo_pipes()
1673 static void i9xx_enable_pll(struct intel_crtc *crtc) in i9xx_enable_pll() argument
1675 struct drm_device *dev = crtc->base.dev; in i9xx_enable_pll()
1677 int reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1678 u32 dpll = crtc->config->dpll_hw_state.dpll; in i9xx_enable_pll()
1680 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_enable_pll()
1687 assert_panel_unlocked(dev_priv, crtc->pipe); in i9xx_enable_pll()
1698 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll()
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1709 I915_WRITE(DPLL_MD(crtc->pipe), in i9xx_enable_pll()
1710 crtc->config->dpll_hw_state.dpll_md); in i9xx_enable_pll()
1741 static void i9xx_disable_pll(struct intel_crtc *crtc) in i9xx_disable_pll() argument
1743 struct drm_device *dev = crtc->base.dev; in i9xx_disable_pll()
1745 enum pipe pipe = crtc->pipe; in i9xx_disable_pll()
1749 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && in i9xx_disable_pll()
1851 static void intel_prepare_shared_dpll(struct intel_crtc *crtc) in intel_prepare_shared_dpll() argument
1853 struct drm_device *dev = crtc->base.dev; in intel_prepare_shared_dpll()
1855 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_prepare_shared_dpll()
1878 static void intel_enable_shared_dpll(struct intel_crtc *crtc) in intel_enable_shared_dpll() argument
1880 struct drm_device *dev = crtc->base.dev; in intel_enable_shared_dpll()
1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_enable_shared_dpll()
1892 crtc->base.base.id); in intel_enable_shared_dpll()
1908 static void intel_disable_shared_dpll(struct intel_crtc *crtc) in intel_disable_shared_dpll() argument
1910 struct drm_device *dev = crtc->base.dev; in intel_disable_shared_dpll()
1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_disable_shared_dpll()
1924 crtc->base.base.id); in intel_disable_shared_dpll()
1947 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in ironlake_enable_pch_transcoder() local
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_enable_pch_transcoder()
2084 static void intel_enable_pipe(struct intel_crtc *crtc) in intel_enable_pipe() argument
2086 struct drm_device *dev = crtc->base.dev; in intel_enable_pipe()
2088 enum pipe pipe = crtc->pipe; in intel_enable_pipe()
2110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) in intel_enable_pipe()
2115 if (crtc->config->has_pch_encoder) { in intel_enable_pipe()
2146 static void intel_disable_pipe(struct intel_crtc *crtc) in intel_disable_pipe() argument
2148 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_disable_pipe()
2149 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; in intel_disable_pipe()
2150 enum pipe pipe = crtc->pipe; in intel_disable_pipe()
2171 if (crtc->config->double_wide) in intel_disable_pipe()
2181 intel_wait_for_pipe_off(crtc); in intel_disable_pipe()
2206 struct drm_crtc *crtc) in intel_enable_primary_hw_plane() argument
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_enable_primary_hw_plane()
2220 dev_priv->display.update_primary_plane(crtc, plane->fb, in intel_enable_primary_hw_plane()
2221 crtc->x, crtc->y); in intel_enable_primary_hw_plane()
2240 struct drm_crtc *crtc) in intel_disable_primary_hw_plane() argument
2244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_disable_primary_hw_plane()
2254 dev_priv->display.update_primary_plane(crtc, plane->fb, in intel_disable_primary_hw_plane()
2255 crtc->x, crtc->y); in intel_disable_primary_hw_plane()
2540 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, in intel_alloc_initial_plane_obj() argument
2543 struct drm_device *dev = crtc->base.dev; in intel_alloc_initial_plane_obj()
2659 primary->state->crtc = &intel_crtc->base; in intel_find_initial_plane_obj()
2660 primary->crtc = &intel_crtc->base; in intel_find_initial_plane_obj()
2665 static void i9xx_update_primary_plane(struct drm_crtc *crtc, in i9xx_update_primary_plane() argument
2669 struct drm_device *dev = crtc->dev; in i9xx_update_primary_plane()
2671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_primary_plane()
2768 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { in i9xx_update_primary_plane()
2794 static void ironlake_update_primary_plane(struct drm_crtc *crtc, in ironlake_update_primary_plane() argument
2798 struct drm_device *dev = crtc->dev; in ironlake_update_primary_plane()
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_update_primary_plane()
2867 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { in ironlake_update_primary_plane()
2941 static void skylake_update_primary_plane(struct drm_crtc *crtc, in skylake_update_primary_plane() argument
2945 struct drm_device *dev = crtc->dev; in skylake_update_primary_plane()
2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in skylake_update_primary_plane()
3012 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) in skylake_update_primary_plane()
3018 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj); in skylake_update_primary_plane()
3034 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, in intel_pipe_set_base_atomic() argument
3037 struct drm_device *dev = crtc->dev; in intel_pipe_set_base_atomic()
3043 dev_priv->display.update_primary_plane(crtc, fb, x, y); in intel_pipe_set_base_atomic()
3050 struct drm_crtc *crtc; in intel_complete_page_flips() local
3052 for_each_crtc(dev, crtc) { in intel_complete_page_flips()
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_complete_page_flips()
3064 struct drm_crtc *crtc; in intel_update_primary_planes() local
3066 for_each_crtc(dev, crtc) { in intel_update_primary_planes()
3067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_update_primary_planes()
3069 drm_modeset_lock(&crtc->mutex, NULL); in intel_update_primary_planes()
3075 if (intel_crtc->active && crtc->primary->fb) in intel_update_primary_planes()
3076 dev_priv->display.update_primary_plane(crtc, in intel_update_primary_planes()
3077 crtc->primary->fb, in intel_update_primary_planes()
3078 crtc->x, in intel_update_primary_planes()
3079 crtc->y); in intel_update_primary_planes()
3080 drm_modeset_unlock(&crtc->mutex); in intel_update_primary_planes()
3087 struct intel_crtc *crtc; in intel_prepare_reset() local
3103 for_each_intel_crtc(dev, crtc) { in intel_prepare_reset()
3104 if (crtc->active) in intel_prepare_reset()
3105 dev_priv->display.crtc_disable(&crtc->base); in intel_prepare_reset()
3180 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) in intel_crtc_has_pending_flip() argument
3182 struct drm_device *dev = crtc->dev; in intel_crtc_has_pending_flip()
3184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_has_pending_flip()
3192 pending = to_intel_crtc(crtc)->unpin_work != NULL; in intel_crtc_has_pending_flip()
3198 static void intel_update_pipe_size(struct intel_crtc *crtc) in intel_update_pipe_size() argument
3200 struct drm_device *dev = crtc->base.dev; in intel_update_pipe_size()
3221 adjusted_mode = &crtc->config->base.adjusted_mode; in intel_update_pipe_size()
3223 I915_WRITE(PIPESRC(crtc->pipe), in intel_update_pipe_size()
3226 if (!crtc->config->pch_pfit.enabled && in intel_update_pipe_size()
3227 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || in intel_update_pipe_size()
3228 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { in intel_update_pipe_size()
3229 I915_WRITE(PF_CTL(crtc->pipe), 0); in intel_update_pipe_size()
3230 I915_WRITE(PF_WIN_POS(crtc->pipe), 0); in intel_update_pipe_size()
3231 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); in intel_update_pipe_size()
3233 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; in intel_update_pipe_size()
3234 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; in intel_update_pipe_size()
3237 static void intel_fdi_normal_train(struct drm_crtc *crtc) in intel_fdi_normal_train() argument
3239 struct drm_device *dev = crtc->dev; in intel_fdi_normal_train()
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_fdi_normal_train()
3279 static void ironlake_fdi_link_train(struct drm_crtc *crtc) in ironlake_fdi_link_train() argument
3281 struct drm_device *dev = crtc->dev; in ironlake_fdi_link_train()
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_link_train()
3379 static void gen6_fdi_link_train(struct drm_crtc *crtc) in gen6_fdi_link_train() argument
3381 struct drm_device *dev = crtc->dev; in gen6_fdi_link_train()
3383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in gen6_fdi_link_train()
3511 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) in ivb_manual_fdi_link_train() argument
3513 struct drm_device *dev = crtc->dev; in ivb_manual_fdi_link_train()
3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ivb_manual_fdi_link_train()
3695 static void ironlake_fdi_disable(struct drm_crtc *crtc) in ironlake_fdi_disable() argument
3697 struct drm_device *dev = crtc->dev; in ironlake_fdi_disable()
3699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_disable()
3749 struct intel_crtc *crtc; in intel_has_pending_fb_unpin() local
3758 for_each_intel_crtc(dev, crtc) { in intel_has_pending_fb_unpin()
3759 if (atomic_read(&crtc->unpin_work_count) == 0) in intel_has_pending_fb_unpin()
3762 if (crtc->unpin_work) in intel_has_pending_fb_unpin()
3763 intel_wait_for_vblank(dev, crtc->pipe); in intel_has_pending_fb_unpin()
3794 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) in intel_crtc_wait_for_pending_flips() argument
3796 struct drm_device *dev = crtc->dev; in intel_crtc_wait_for_pending_flips()
3801 !intel_crtc_has_pending_flip(crtc), in intel_crtc_wait_for_pending_flips()
3803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_wait_for_pending_flips()
3813 if (crtc->primary->fb) { in intel_crtc_wait_for_pending_flips()
3815 intel_finish_fb(crtc->primary->fb); in intel_crtc_wait_for_pending_flips()
3821 static void lpt_program_iclkip(struct drm_crtc *crtc) in lpt_program_iclkip() argument
3823 struct drm_device *dev = crtc->dev; in lpt_program_iclkip()
3825 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; in lpt_program_iclkip()
3909 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, in ironlake_pch_transcoder_set_timings() argument
3912 struct drm_device *dev = crtc->base.dev; in ironlake_pch_transcoder_set_timings()
3914 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; in ironlake_pch_transcoder_set_timings()
3985 static void ironlake_pch_enable(struct drm_crtc *crtc) in ironlake_pch_enable() argument
3987 struct drm_device *dev = crtc->dev; in ironlake_pch_enable()
3989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_pch_enable()
4004 dev_priv->display.fdi_link_train(crtc); in ironlake_pch_enable()
4034 intel_fdi_normal_train(crtc); in ironlake_pch_enable()
4048 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) in ironlake_pch_enable()
4050 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) in ironlake_pch_enable()
4053 switch (intel_trans_dp_port_sel(crtc)) { in ironlake_pch_enable()
4073 static void lpt_pch_enable(struct drm_crtc *crtc) in lpt_pch_enable() argument
4075 struct drm_device *dev = crtc->dev; in lpt_pch_enable()
4077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in lpt_pch_enable()
4082 lpt_program_iclkip(crtc); in lpt_pch_enable()
4090 void intel_put_shared_dpll(struct intel_crtc *crtc) in intel_put_shared_dpll() argument
4092 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_put_shared_dpll()
4097 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { in intel_put_shared_dpll()
4102 pll->config.crtc_mask &= ~(1 << crtc->pipe); in intel_put_shared_dpll()
4108 crtc->config->shared_dpll = DPLL_ID_PRIVATE; in intel_put_shared_dpll()
4111 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, in intel_get_shared_dpll() argument
4114 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_get_shared_dpll()
4120 i = (enum intel_dpll_id) crtc->pipe; in intel_get_shared_dpll()
4124 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4142 crtc->base.base.id, pll->name, in intel_get_shared_dpll()
4154 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4167 pipe_name(crtc->pipe)); in intel_get_shared_dpll()
4169 pll->new_config->crtc_mask |= 1 << crtc->pipe; in intel_get_shared_dpll()
4256 static void skylake_pfit_enable(struct intel_crtc *crtc) in skylake_pfit_enable() argument
4258 struct drm_device *dev = crtc->base.dev; in skylake_pfit_enable()
4260 int pipe = crtc->pipe; in skylake_pfit_enable()
4262 if (crtc->config->pch_pfit.enabled) { in skylake_pfit_enable()
4264 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); in skylake_pfit_enable()
4265 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); in skylake_pfit_enable()
4269 static void ironlake_pfit_enable(struct intel_crtc *crtc) in ironlake_pfit_enable() argument
4271 struct drm_device *dev = crtc->base.dev; in ironlake_pfit_enable()
4273 int pipe = crtc->pipe; in ironlake_pfit_enable()
4275 if (crtc->config->pch_pfit.enabled) { in ironlake_pfit_enable()
4285 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); in ironlake_pfit_enable()
4286 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); in ironlake_pfit_enable()
4290 static void intel_enable_sprite_planes(struct drm_crtc *crtc) in intel_enable_sprite_planes() argument
4292 struct drm_device *dev = crtc->dev; in intel_enable_sprite_planes()
4293 enum pipe pipe = to_intel_crtc(crtc)->pipe; in intel_enable_sprite_planes()
4322 static void intel_disable_sprite_planes(struct drm_crtc *crtc) in intel_disable_sprite_planes() argument
4324 struct drm_device *dev = crtc->dev; in intel_disable_sprite_planes()
4325 enum pipe pipe = to_intel_crtc(crtc)->pipe; in intel_disable_sprite_planes()
4336 void hsw_enable_ips(struct intel_crtc *crtc) in hsw_enable_ips() argument
4338 struct drm_device *dev = crtc->base.dev; in hsw_enable_ips()
4341 if (!crtc->config->ips_enabled) in hsw_enable_ips()
4345 intel_wait_for_vblank(dev, crtc->pipe); in hsw_enable_ips()
4347 assert_plane_enabled(dev_priv, crtc->plane); in hsw_enable_ips()
4369 void hsw_disable_ips(struct intel_crtc *crtc) in hsw_disable_ips() argument
4371 struct drm_device *dev = crtc->base.dev; in hsw_disable_ips()
4374 if (!crtc->config->ips_enabled) in hsw_disable_ips()
4377 assert_plane_enabled(dev_priv, crtc->plane); in hsw_disable_ips()
4391 intel_wait_for_vblank(dev, crtc->pipe); in hsw_disable_ips()
4395 static void intel_crtc_load_lut(struct drm_crtc *crtc) in intel_crtc_load_lut() argument
4397 struct drm_device *dev = crtc->dev; in intel_crtc_load_lut()
4399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_load_lut()
4406 if (!crtc->state->enable || !intel_crtc->active) in intel_crtc_load_lut()
4459 static void intel_crtc_enable_planes(struct drm_crtc *crtc) in intel_crtc_enable_planes() argument
4461 struct drm_device *dev = crtc->dev; in intel_crtc_enable_planes()
4462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_enable_planes()
4465 intel_enable_primary_hw_plane(crtc->primary, crtc); in intel_crtc_enable_planes()
4466 intel_enable_sprite_planes(crtc); in intel_crtc_enable_planes()
4467 intel_crtc_update_cursor(crtc, true); in intel_crtc_enable_planes()
4484 static void intel_crtc_disable_planes(struct drm_crtc *crtc) in intel_crtc_disable_planes() argument
4486 struct drm_device *dev = crtc->dev; in intel_crtc_disable_planes()
4488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_disable_planes()
4491 intel_crtc_wait_for_pending_flips(crtc); in intel_crtc_disable_planes()
4493 if (dev_priv->fbc.crtc == intel_crtc) in intel_crtc_disable_planes()
4499 intel_crtc_update_cursor(crtc, false); in intel_crtc_disable_planes()
4500 intel_disable_sprite_planes(crtc); in intel_crtc_disable_planes()
4501 intel_disable_primary_hw_plane(crtc->primary, crtc); in intel_crtc_disable_planes()
4511 static void ironlake_crtc_enable(struct drm_crtc *crtc) in ironlake_crtc_enable() argument
4513 struct drm_device *dev = crtc->dev; in ironlake_crtc_enable()
4515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_enable()
4519 WARN_ON(!crtc->state->enable); in ironlake_crtc_enable()
4537 ironlake_set_pipeconf(crtc); in ironlake_crtc_enable()
4544 for_each_encoder_on_crtc(dev, crtc, encoder) in ironlake_crtc_enable()
4564 intel_crtc_load_lut(crtc); in ironlake_crtc_enable()
4566 intel_update_watermarks(crtc); in ironlake_crtc_enable()
4570 ironlake_pch_enable(crtc); in ironlake_crtc_enable()
4572 assert_vblank_disabled(crtc); in ironlake_crtc_enable()
4573 drm_crtc_vblank_on(crtc); in ironlake_crtc_enable()
4575 for_each_encoder_on_crtc(dev, crtc, encoder) in ironlake_crtc_enable()
4581 intel_crtc_enable_planes(crtc); in ironlake_crtc_enable()
4585 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) in hsw_crtc_supports_ips() argument
4587 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
4596 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) in haswell_mode_set_planes_workaround() argument
4598 struct drm_device *dev = crtc->base.dev; in haswell_mode_set_planes_workaround()
4604 if (!crtc_it->active || crtc_it == crtc) in haswell_mode_set_planes_workaround()
4619 static void haswell_crtc_enable(struct drm_crtc *crtc) in haswell_crtc_enable() argument
4621 struct drm_device *dev = crtc->dev; in haswell_crtc_enable()
4623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_enable()
4627 WARN_ON(!crtc->state->enable); in haswell_crtc_enable()
4650 haswell_set_pipeconf(crtc); in haswell_crtc_enable()
4652 intel_set_pipe_csc(crtc); in haswell_crtc_enable()
4657 for_each_encoder_on_crtc(dev, crtc, encoder) in haswell_crtc_enable()
4664 dev_priv->display.fdi_link_train(crtc); in haswell_crtc_enable()
4678 intel_crtc_load_lut(crtc); in haswell_crtc_enable()
4680 intel_ddi_set_pipe_settings(crtc); in haswell_crtc_enable()
4681 intel_ddi_enable_transcoder_func(crtc); in haswell_crtc_enable()
4683 intel_update_watermarks(crtc); in haswell_crtc_enable()
4687 lpt_pch_enable(crtc); in haswell_crtc_enable()
4690 intel_ddi_set_vc_payload_alloc(crtc, true); in haswell_crtc_enable()
4692 assert_vblank_disabled(crtc); in haswell_crtc_enable()
4693 drm_crtc_vblank_on(crtc); in haswell_crtc_enable()
4695 for_each_encoder_on_crtc(dev, crtc, encoder) { in haswell_crtc_enable()
4703 intel_crtc_enable_planes(crtc); in haswell_crtc_enable()
4706 static void skylake_pfit_disable(struct intel_crtc *crtc) in skylake_pfit_disable() argument
4708 struct drm_device *dev = crtc->base.dev; in skylake_pfit_disable()
4710 int pipe = crtc->pipe; in skylake_pfit_disable()
4714 if (crtc->config->pch_pfit.enabled) { in skylake_pfit_disable()
4721 static void ironlake_pfit_disable(struct intel_crtc *crtc) in ironlake_pfit_disable() argument
4723 struct drm_device *dev = crtc->base.dev; in ironlake_pfit_disable()
4725 int pipe = crtc->pipe; in ironlake_pfit_disable()
4729 if (crtc->config->pch_pfit.enabled) { in ironlake_pfit_disable()
4736 static void ironlake_crtc_disable(struct drm_crtc *crtc) in ironlake_crtc_disable() argument
4738 struct drm_device *dev = crtc->dev; in ironlake_crtc_disable()
4740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_disable()
4748 intel_crtc_disable_planes(crtc); in ironlake_crtc_disable()
4750 for_each_encoder_on_crtc(dev, crtc, encoder) in ironlake_crtc_disable()
4753 drm_crtc_vblank_off(crtc); in ironlake_crtc_disable()
4754 assert_vblank_disabled(crtc); in ironlake_crtc_disable()
4763 for_each_encoder_on_crtc(dev, crtc, encoder) in ironlake_crtc_disable()
4768 ironlake_fdi_disable(crtc); in ironlake_crtc_disable()
4794 intel_update_watermarks(crtc); in ironlake_crtc_disable()
4801 static void haswell_crtc_disable(struct drm_crtc *crtc) in haswell_crtc_disable() argument
4803 struct drm_device *dev = crtc->dev; in haswell_crtc_disable()
4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_disable()
4812 intel_crtc_disable_planes(crtc); in haswell_crtc_disable()
4814 for_each_encoder_on_crtc(dev, crtc, encoder) { in haswell_crtc_disable()
4819 drm_crtc_vblank_off(crtc); in haswell_crtc_disable()
4820 assert_vblank_disabled(crtc); in haswell_crtc_disable()
4828 intel_ddi_set_vc_payload_alloc(crtc, false); in haswell_crtc_disable()
4841 intel_ddi_fdi_disable(crtc); in haswell_crtc_disable()
4844 for_each_encoder_on_crtc(dev, crtc, encoder) in haswell_crtc_disable()
4849 intel_update_watermarks(crtc); in haswell_crtc_disable()
4859 static void ironlake_crtc_off(struct drm_crtc *crtc) in ironlake_crtc_off() argument
4861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_off()
4866 static void i9xx_pfit_enable(struct intel_crtc *crtc) in i9xx_pfit_enable() argument
4868 struct drm_device *dev = crtc->base.dev; in i9xx_pfit_enable()
4870 struct intel_crtc_state *pipe_config = crtc->config; in i9xx_pfit_enable()
4880 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_enable()
4887 I915_WRITE(BCLRPAT(crtc->pipe), 0); in i9xx_pfit_enable()
4938 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) in get_crtc_power_domains() argument
4940 struct drm_device *dev = crtc->dev; in get_crtc_power_domains()
4942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in get_crtc_power_domains()
4955 for_each_encoder_on_crtc(dev, crtc, intel_encoder) in get_crtc_power_domains()
4966 struct intel_crtc *crtc; in modeset_update_crtc_power_domains() local
4972 for_each_intel_crtc(dev, crtc) { in modeset_update_crtc_power_domains()
4975 if (!crtc->base.state->enable) in modeset_update_crtc_power_domains()
4978 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); in modeset_update_crtc_power_domains()
4980 for_each_power_domain(domain, pipe_domains[crtc->pipe]) in modeset_update_crtc_power_domains()
4987 for_each_intel_crtc(dev, crtc) { in modeset_update_crtc_power_domains()
4990 for_each_power_domain(domain, crtc->enabled_power_domains) in modeset_update_crtc_power_domains()
4993 crtc->enabled_power_domains = pipe_domains[crtc->pipe]; in modeset_update_crtc_power_domains()
5263 static void valleyview_crtc_enable(struct drm_crtc *crtc) in valleyview_crtc_enable() argument
5265 struct drm_device *dev = crtc->dev; in valleyview_crtc_enable()
5267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in valleyview_crtc_enable()
5272 WARN_ON(!crtc->state->enable); in valleyview_crtc_enable()
5304 for_each_encoder_on_crtc(dev, crtc, encoder) in valleyview_crtc_enable()
5315 for_each_encoder_on_crtc(dev, crtc, encoder) in valleyview_crtc_enable()
5321 intel_crtc_load_lut(crtc); in valleyview_crtc_enable()
5323 intel_update_watermarks(crtc); in valleyview_crtc_enable()
5326 assert_vblank_disabled(crtc); in valleyview_crtc_enable()
5327 drm_crtc_vblank_on(crtc); in valleyview_crtc_enable()
5329 for_each_encoder_on_crtc(dev, crtc, encoder) in valleyview_crtc_enable()
5332 intel_crtc_enable_planes(crtc); in valleyview_crtc_enable()
5338 static void i9xx_set_pll_dividers(struct intel_crtc *crtc) in i9xx_set_pll_dividers() argument
5340 struct drm_device *dev = crtc->base.dev; in i9xx_set_pll_dividers()
5343 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
5344 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
5347 static void i9xx_crtc_enable(struct drm_crtc *crtc) in i9xx_crtc_enable() argument
5349 struct drm_device *dev = crtc->dev; in i9xx_crtc_enable()
5351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_enable()
5355 WARN_ON(!crtc->state->enable); in i9xx_crtc_enable()
5374 for_each_encoder_on_crtc(dev, crtc, encoder) in i9xx_crtc_enable()
5382 intel_crtc_load_lut(crtc); in i9xx_crtc_enable()
5384 intel_update_watermarks(crtc); in i9xx_crtc_enable()
5387 assert_vblank_disabled(crtc); in i9xx_crtc_enable()
5388 drm_crtc_vblank_on(crtc); in i9xx_crtc_enable()
5390 for_each_encoder_on_crtc(dev, crtc, encoder) in i9xx_crtc_enable()
5393 intel_crtc_enable_planes(crtc); in i9xx_crtc_enable()
5409 static void i9xx_pfit_disable(struct intel_crtc *crtc) in i9xx_pfit_disable() argument
5411 struct drm_device *dev = crtc->base.dev; in i9xx_pfit_disable()
5414 if (!crtc->config->gmch_pfit.control) in i9xx_pfit_disable()
5417 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_disable()
5424 static void i9xx_crtc_disable(struct drm_crtc *crtc) in i9xx_crtc_disable() argument
5426 struct drm_device *dev = crtc->dev; in i9xx_crtc_disable()
5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_disable()
5454 intel_crtc_disable_planes(crtc); in i9xx_crtc_disable()
5464 for_each_encoder_on_crtc(dev, crtc, encoder) in i9xx_crtc_disable()
5467 drm_crtc_vblank_off(crtc); in i9xx_crtc_disable()
5468 assert_vblank_disabled(crtc); in i9xx_crtc_disable()
5474 for_each_encoder_on_crtc(dev, crtc, encoder) in i9xx_crtc_disable()
5491 intel_update_watermarks(crtc); in i9xx_crtc_disable()
5498 static void i9xx_crtc_off(struct drm_crtc *crtc) in i9xx_crtc_off() argument
5503 void intel_crtc_control(struct drm_crtc *crtc, bool enable) in intel_crtc_control() argument
5505 struct drm_device *dev = crtc->dev; in intel_crtc_control()
5507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_control()
5513 domains = get_crtc_power_domains(crtc); in intel_crtc_control()
5518 dev_priv->display.crtc_enable(crtc); in intel_crtc_control()
5522 dev_priv->display.crtc_disable(crtc); in intel_crtc_control()
5535 void intel_crtc_update_dpms(struct drm_crtc *crtc) in intel_crtc_update_dpms() argument
5537 struct drm_device *dev = crtc->dev; in intel_crtc_update_dpms()
5541 for_each_encoder_on_crtc(dev, crtc, intel_encoder) in intel_crtc_update_dpms()
5544 intel_crtc_control(crtc, enable); in intel_crtc_update_dpms()
5547 static void intel_crtc_disable(struct drm_crtc *crtc) in intel_crtc_disable() argument
5549 struct drm_device *dev = crtc->dev; in intel_crtc_disable()
5554 WARN_ON(!crtc->state->enable); in intel_crtc_disable()
5556 dev_priv->display.crtc_disable(crtc); in intel_crtc_disable()
5557 dev_priv->display.off(crtc); in intel_crtc_disable()
5559 crtc->primary->funcs->disable_plane(crtc->primary); in intel_crtc_disable()
5563 if (!connector->encoder || !connector->encoder->crtc) in intel_crtc_disable()
5566 if (connector->encoder->crtc != crtc) in intel_crtc_disable()
5590 intel_crtc_update_dpms(encoder->base.crtc); in intel_encoder_dpms()
5594 intel_crtc_update_dpms(encoder->base.crtc); in intel_encoder_dpms()
5604 struct drm_crtc *crtc; in intel_connector_check_state() local
5623 if (I915_STATE_WARN_ON(!encoder->base.crtc)) in intel_connector_check_state()
5626 crtc = encoder->base.crtc; in intel_connector_check_state()
5628 I915_STATE_WARN(!crtc->state->enable, in intel_connector_check_state()
5630 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); in intel_connector_check_state()
5631 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, in intel_connector_check_state()
5698 struct intel_crtc *crtc = in pipe_required_fdi_lanes() local
5701 if (crtc->base.state->enable && in pipe_required_fdi_lanes()
5702 crtc->config->has_pch_encoder) in pipe_required_fdi_lanes()
5703 return crtc->config->fdi_lanes; in pipe_required_fdi_lanes()
5807 static void hsw_compute_ips_config(struct intel_crtc *crtc, in hsw_compute_ips_config() argument
5811 hsw_crtc_supports_ips(crtc) && in hsw_compute_ips_config()
5815 static int intel_crtc_compute_config(struct intel_crtc *crtc, in intel_crtc_compute_config() argument
5818 struct drm_device *dev = crtc->base.dev; in intel_crtc_compute_config()
5834 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && in intel_crtc_compute_config()
5870 hsw_compute_ips_config(crtc, pipe_config); in intel_crtc_compute_config()
5873 return ironlake_fdi_compute_config(crtc, pipe_config); in intel_crtc_compute_config()
6032 struct drm_device *dev = crtc_state->base.crtc->dev; in i9xx_get_refclk()
6063 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, in i9xx_update_pll_dividers() argument
6067 struct drm_device *dev = crtc->base.dev; in i9xx_update_pll_dividers()
6082 crtc->lowfreq_avail = false; in i9xx_update_pll_dividers()
6086 crtc->lowfreq_avail = true; in i9xx_update_pll_dividers()
6121 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_set_m_n() argument
6124 struct drm_device *dev = crtc->base.dev; in intel_pch_transcoder_set_m_n()
6126 int pipe = crtc->pipe; in intel_pch_transcoder_set_m_n()
6134 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_set_m_n() argument
6138 struct drm_device *dev = crtc->base.dev; in intel_cpu_transcoder_set_m_n()
6140 int pipe = crtc->pipe; in intel_cpu_transcoder_set_m_n()
6141 enum transcoder transcoder = crtc->config->cpu_transcoder; in intel_cpu_transcoder_set_m_n()
6153 crtc->config->has_drrs) { in intel_cpu_transcoder_set_m_n()
6168 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) in intel_dp_set_m_n() argument
6173 dp_m_n = &crtc->config->dp_m_n; in intel_dp_set_m_n()
6174 dp_m2_n2 = &crtc->config->dp_m2_n2; in intel_dp_set_m_n()
6181 dp_m_n = &crtc->config->dp_m2_n2; in intel_dp_set_m_n()
6187 if (crtc->config->has_pch_encoder) in intel_dp_set_m_n()
6188 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); in intel_dp_set_m_n()
6190 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); in intel_dp_set_m_n()
6193 static void vlv_update_pll(struct intel_crtc *crtc, in vlv_update_pll() argument
6206 if (crtc->pipe == PIPE_B) in vlv_update_pll()
6216 static void vlv_prepare_pll(struct intel_crtc *crtc, in vlv_prepare_pll() argument
6219 struct drm_device *dev = crtc->base.dev; in vlv_prepare_pll()
6221 int pipe = crtc->pipe; in vlv_prepare_pll()
6270 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || in vlv_prepare_pll()
6271 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) in vlv_prepare_pll()
6298 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || in vlv_prepare_pll()
6299 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) in vlv_prepare_pll()
6307 static void chv_update_pll(struct intel_crtc *crtc, in chv_update_pll() argument
6313 if (crtc->pipe != PIPE_A) in chv_update_pll()
6320 static void chv_prepare_pll(struct intel_crtc *crtc, in chv_prepare_pll() argument
6323 struct drm_device *dev = crtc->base.dev; in chv_prepare_pll()
6325 int pipe = crtc->pipe; in chv_prepare_pll()
6326 int dpll_reg = DPLL(crtc->pipe); in chv_prepare_pll()
6438 struct intel_crtc *crtc = in vlv_force_pll_on() local
6441 .base.crtc = &crtc->base, in vlv_force_pll_on()
6447 chv_update_pll(crtc, &pipe_config); in vlv_force_pll_on()
6448 chv_prepare_pll(crtc, &pipe_config); in vlv_force_pll_on()
6449 chv_enable_pll(crtc, &pipe_config); in vlv_force_pll_on()
6451 vlv_update_pll(crtc, &pipe_config); in vlv_force_pll_on()
6452 vlv_prepare_pll(crtc, &pipe_config); in vlv_force_pll_on()
6453 vlv_enable_pll(crtc, &pipe_config); in vlv_force_pll_on()
6473 static void i9xx_update_pll(struct intel_crtc *crtc, in i9xx_update_pll() argument
6478 struct drm_device *dev = crtc->base.dev; in i9xx_update_pll()
6484 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); in i9xx_update_pll()
6550 static void i8xx_update_pll(struct intel_crtc *crtc, in i8xx_update_pll() argument
6555 struct drm_device *dev = crtc->base.dev; in i8xx_update_pll()
6560 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); in i8xx_update_pll()
6657 static void intel_get_pipe_timings(struct intel_crtc *crtc, in intel_get_pipe_timings() argument
6660 struct drm_device *dev = crtc->base.dev; in intel_get_pipe_timings()
6691 tmp = I915_READ(PIPESRC(crtc->pipe)); in intel_get_pipe_timings()
6781 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, in i9xx_crtc_compute_clock() argument
6784 struct drm_device *dev = crtc->base.dev; in i9xx_crtc_compute_clock()
6801 if (connector_state->crtc != &crtc->base) in i9xx_crtc_compute_clock()
6863 i8xx_update_pll(crtc, crtc_state, in i9xx_crtc_compute_clock()
6867 chv_update_pll(crtc, crtc_state); in i9xx_crtc_compute_clock()
6869 vlv_update_pll(crtc, crtc_state); in i9xx_crtc_compute_clock()
6871 i9xx_update_pll(crtc, crtc_state, in i9xx_crtc_compute_clock()
6879 static void i9xx_get_pfit_config(struct intel_crtc *crtc, in i9xx_get_pfit_config() argument
6882 struct drm_device *dev = crtc->base.dev; in i9xx_get_pfit_config()
6895 if (crtc->pipe != PIPE_B) in i9xx_get_pfit_config()
6898 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) in i9xx_get_pfit_config()
6909 static void vlv_crtc_clock_get(struct intel_crtc *crtc, in vlv_crtc_clock_get() argument
6912 struct drm_device *dev = crtc->base.dev; in vlv_crtc_clock_get()
6940 i9xx_get_initial_plane_config(struct intel_crtc *crtc, in i9xx_get_initial_plane_config() argument
6943 struct drm_device *dev = crtc->base.dev; in i9xx_get_initial_plane_config()
6946 int pipe = crtc->pipe, plane = crtc->plane; in i9xx_get_initial_plane_config()
7008 static void chv_crtc_clock_get(struct intel_crtc *crtc, in chv_crtc_clock_get() argument
7011 struct drm_device *dev = crtc->base.dev; in chv_crtc_clock_get()
7038 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, in i9xx_get_pipe_config() argument
7041 struct drm_device *dev = crtc->base.dev; in i9xx_get_pipe_config()
7046 POWER_DOMAIN_PIPE(crtc->pipe))) in i9xx_get_pipe_config()
7049 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
7052 tmp = I915_READ(PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
7078 intel_get_pipe_timings(crtc, pipe_config); in i9xx_get_pipe_config()
7080 i9xx_get_pfit_config(crtc, pipe_config); in i9xx_get_pipe_config()
7083 tmp = I915_READ(DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
7089 tmp = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7099 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7109 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
7110 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
7119 chv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
7121 vlv_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
7123 i9xx_crtc_clock_get(crtc, pipe_config); in i9xx_get_pipe_config()
7481 struct drm_device *dev = crtc_state->base.crtc->dev; in ironlake_get_refclk()
7494 if (connector_state->crtc != crtc_state->base.crtc) in ironlake_get_refclk()
7518 static void ironlake_set_pipeconf(struct drm_crtc *crtc) in ironlake_set_pipeconf() argument
7520 struct drm_i915_private *dev_priv = crtc->dev->dev_private; in ironlake_set_pipeconf()
7521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_set_pipeconf()
7567 static void intel_set_pipe_csc(struct drm_crtc *crtc) in intel_set_pipe_csc() argument
7569 struct drm_device *dev = crtc->dev; in intel_set_pipe_csc()
7571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_set_pipe_csc()
7624 static void haswell_set_pipeconf(struct drm_crtc *crtc) in haswell_set_pipeconf() argument
7626 struct drm_device *dev = crtc->dev; in haswell_set_pipeconf()
7628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_set_pipeconf()
7677 static bool ironlake_compute_clocks(struct drm_crtc *crtc, in ironlake_compute_clocks() argument
7683 struct drm_device *dev = crtc->dev; in ironlake_compute_clocks()
7743 struct drm_crtc *crtc = &intel_crtc->base; in ironlake_compute_dpll() local
7744 struct drm_device *dev = crtc->dev; in ironlake_compute_dpll()
7758 if (connector_state->crtc != crtc_state->base.crtc) in ironlake_compute_dpll()
7837 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, in ironlake_crtc_compute_clock() argument
7840 struct drm_device *dev = crtc->base.dev; in ironlake_crtc_compute_clock()
7847 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); in ironlake_crtc_compute_clock()
7852 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, in ironlake_crtc_compute_clock()
7873 dpll = ironlake_compute_dpll(crtc, crtc_state, in ironlake_crtc_compute_clock()
7884 pll = intel_get_shared_dpll(crtc, crtc_state); in ironlake_crtc_compute_clock()
7887 pipe_name(crtc->pipe)); in ironlake_crtc_compute_clock()
7893 crtc->lowfreq_avail = true; in ironlake_crtc_compute_clock()
7895 crtc->lowfreq_avail = false; in ironlake_crtc_compute_clock()
7900 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_get_m_n() argument
7903 struct drm_device *dev = crtc->base.dev; in intel_pch_transcoder_get_m_n()
7905 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_get_m_n()
7916 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_get_m_n() argument
7921 struct drm_device *dev = crtc->base.dev; in intel_cpu_transcoder_get_m_n()
7923 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_get_m_n()
7938 crtc->config->has_drrs) { in intel_cpu_transcoder_get_m_n()
7958 void intel_dp_get_m_n(struct intel_crtc *crtc, in intel_dp_get_m_n() argument
7962 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); in intel_dp_get_m_n()
7964 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in intel_dp_get_m_n()
7969 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, in ironlake_get_fdi_m_n_config() argument
7972 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, in ironlake_get_fdi_m_n_config()
7976 static void skylake_get_pfit_config(struct intel_crtc *crtc, in skylake_get_pfit_config() argument
7979 struct drm_device *dev = crtc->base.dev; in skylake_get_pfit_config()
7983 tmp = I915_READ(PS_CTL(crtc->pipe)); in skylake_get_pfit_config()
7987 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); in skylake_get_pfit_config()
7988 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); in skylake_get_pfit_config()
7993 skylake_get_initial_plane_config(struct intel_crtc *crtc, in skylake_get_initial_plane_config() argument
7996 struct drm_device *dev = crtc->base.dev; in skylake_get_initial_plane_config()
7999 int pipe = crtc->pipe; in skylake_get_initial_plane_config()
8076 static void ironlake_get_pfit_config(struct intel_crtc *crtc, in ironlake_get_pfit_config() argument
8079 struct drm_device *dev = crtc->base.dev; in ironlake_get_pfit_config()
8083 tmp = I915_READ(PF_CTL(crtc->pipe)); in ironlake_get_pfit_config()
8087 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
8088 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
8095 PF_PIPE_SEL_IVB(crtc->pipe)); in ironlake_get_pfit_config()
8101 ironlake_get_initial_plane_config(struct intel_crtc *crtc, in ironlake_get_initial_plane_config() argument
8104 struct drm_device *dev = crtc->base.dev; in ironlake_get_initial_plane_config()
8107 int pipe = crtc->pipe; in ironlake_get_initial_plane_config()
8169 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, in ironlake_get_pipe_config() argument
8172 struct drm_device *dev = crtc->base.dev; in ironlake_get_pipe_config()
8177 POWER_DOMAIN_PIPE(crtc->pipe))) in ironlake_get_pipe_config()
8180 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ironlake_get_pipe_config()
8183 tmp = I915_READ(PIPECONF(crtc->pipe)); in ironlake_get_pipe_config()
8207 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { in ironlake_get_pipe_config()
8212 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); in ironlake_get_pipe_config()
8216 ironlake_get_fdi_m_n_config(crtc, pipe_config); in ironlake_get_pipe_config()
8220 (enum intel_dpll_id) crtc->pipe; in ironlake_get_pipe_config()
8223 if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) in ironlake_get_pipe_config()
8239 ironlake_pch_clock_get(crtc, pipe_config); in ironlake_get_pipe_config()
8244 intel_get_pipe_timings(crtc, pipe_config); in ironlake_get_pipe_config()
8246 ironlake_get_pfit_config(crtc, pipe_config); in ironlake_get_pipe_config()
8254 struct intel_crtc *crtc; in assert_can_disable_lcpll() local
8256 for_each_intel_crtc(dev, crtc) in assert_can_disable_lcpll()
8257 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", in assert_can_disable_lcpll()
8258 pipe_name(crtc->pipe)); in assert_can_disable_lcpll()
8473 static int haswell_crtc_compute_clock(struct intel_crtc *crtc, in haswell_crtc_compute_clock() argument
8476 if (!intel_ddi_pll_select(crtc, crtc_state)) in haswell_crtc_compute_clock()
8479 crtc->lowfreq_avail = false; in haswell_crtc_compute_clock()
8531 static void haswell_get_ddi_port_state(struct intel_crtc *crtc, in haswell_get_ddi_port_state() argument
8534 struct drm_device *dev = crtc->base.dev; in haswell_get_ddi_port_state()
8569 ironlake_get_fdi_m_n_config(crtc, pipe_config); in haswell_get_ddi_port_state()
8573 static bool haswell_get_pipe_config(struct intel_crtc *crtc, in haswell_get_pipe_config() argument
8576 struct drm_device *dev = crtc->base.dev; in haswell_get_pipe_config()
8582 POWER_DOMAIN_PIPE(crtc->pipe))) in haswell_get_pipe_config()
8585 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in haswell_get_pipe_config()
8606 if (trans_edp_pipe == crtc->pipe) in haswell_get_pipe_config()
8618 haswell_get_ddi_port_state(crtc, pipe_config); in haswell_get_pipe_config()
8620 intel_get_pipe_timings(crtc, pipe_config); in haswell_get_pipe_config()
8622 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); in haswell_get_pipe_config()
8625 skylake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
8627 ironlake_get_pfit_config(crtc, pipe_config); in haswell_get_pipe_config()
8631 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && in haswell_get_pipe_config()
8644 static void i845_update_cursor(struct drm_crtc *crtc, u32 base) in i845_update_cursor() argument
8646 struct drm_device *dev = crtc->dev; in i845_update_cursor()
8648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i845_update_cursor()
8706 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) in i9xx_update_cursor() argument
8708 struct drm_device *dev = crtc->dev; in i9xx_update_cursor()
8710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_cursor()
8737 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) in i9xx_update_cursor()
8754 static void intel_crtc_update_cursor(struct drm_crtc *crtc, in intel_crtc_update_cursor() argument
8757 struct drm_device *dev = crtc->dev; in intel_crtc_update_cursor()
8759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_update_cursor()
8761 int x = crtc->cursor_x; in intel_crtc_update_cursor()
8762 int y = crtc->cursor_y; in intel_crtc_update_cursor()
8799 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { in intel_crtc_update_cursor()
8805 i845_update_cursor(crtc, base); in intel_crtc_update_cursor()
8807 i9xx_update_cursor(crtc, base); in intel_crtc_update_cursor()
8847 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, in intel_crtc_gamma_set() argument
8851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_gamma_set()
8859 intel_crtc_load_lut(crtc); in intel_crtc_gamma_set()
8989 struct drm_crtc *crtc = NULL; in intel_get_load_detect_pipe() local
9017 if (encoder->crtc) { in intel_get_load_detect_pipe()
9018 crtc = encoder->crtc; in intel_get_load_detect_pipe()
9020 ret = drm_modeset_lock(&crtc->mutex, ctx); in intel_get_load_detect_pipe()
9023 ret = drm_modeset_lock(&crtc->primary->mutex, ctx); in intel_get_load_detect_pipe()
9048 crtc = possible_crtc; in intel_get_load_detect_pipe()
9055 if (!crtc) { in intel_get_load_detect_pipe()
9060 ret = drm_modeset_lock(&crtc->mutex, ctx); in intel_get_load_detect_pipe()
9063 ret = drm_modeset_lock(&crtc->primary->mutex, ctx); in intel_get_load_detect_pipe()
9066 intel_encoder->new_crtc = to_intel_crtc(crtc); in intel_get_load_detect_pipe()
9069 intel_crtc = to_intel_crtc(crtc); in intel_get_load_detect_pipe()
9088 connector_state->crtc = crtc; in intel_get_load_detect_pipe()
9113 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { in intel_get_load_detect_pipe()
9119 crtc->primary->crtc = crtc; in intel_get_load_detect_pipe()
9126 intel_crtc->new_enabled = crtc->state->enable; in intel_get_load_detect_pipe()
9153 struct drm_crtc *crtc = encoder->crtc; in intel_release_load_detect_pipe() local
9154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_release_load_detect_pipe()
9179 connector_state->crtc = NULL; in intel_release_load_detect_pipe()
9181 intel_set_mode(crtc, NULL, 0, 0, NULL, state); in intel_release_load_detect_pipe()
9220 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, in i9xx_crtc_clock_get() argument
9223 struct drm_device *dev = crtc->base.dev; in i9xx_crtc_clock_get()
9327 static void ironlake_pch_clock_get(struct intel_crtc *crtc, in ironlake_pch_clock_get() argument
9330 struct drm_device *dev = crtc->base.dev; in ironlake_pch_clock_get()
9333 i9xx_crtc_clock_get(crtc, pipe_config); in ironlake_pch_clock_get()
9348 struct drm_crtc *crtc) in intel_crtc_mode_get() argument
9351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_mode_get()
9394 static void intel_decrease_pllclock(struct drm_crtc *crtc) in intel_decrease_pllclock() argument
9396 struct drm_device *dev = crtc->dev; in intel_decrease_pllclock()
9398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_decrease_pllclock()
9447 struct drm_crtc *crtc; in intel_mark_idle() local
9454 for_each_crtc(dev, crtc) { in intel_mark_idle()
9455 if (!crtc->primary->fb) in intel_mark_idle()
9458 intel_decrease_pllclock(crtc); in intel_mark_idle()
9467 static void intel_crtc_set_state(struct intel_crtc *crtc, in intel_crtc_set_state() argument
9470 kfree(crtc->config); in intel_crtc_set_state()
9471 crtc->config = crtc_state; in intel_crtc_set_state()
9472 crtc->base.state = &crtc_state->base; in intel_crtc_set_state()
9475 static void intel_crtc_destroy(struct drm_crtc *crtc) in intel_crtc_destroy() argument
9477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_destroy()
9478 struct drm_device *dev = crtc->dev; in intel_crtc_destroy()
9492 drm_crtc_cleanup(crtc); in intel_crtc_destroy()
9501 struct drm_device *dev = work->crtc->dev; in intel_unpin_work_fn()
9502 enum pipe pipe = to_intel_crtc(work->crtc)->pipe; in intel_unpin_work_fn()
9505 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); in intel_unpin_work_fn()
9517 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); in intel_unpin_work_fn()
9518 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); in intel_unpin_work_fn()
9524 struct drm_crtc *crtc) in do_intel_finish_page_flip() argument
9526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in do_intel_finish_page_flip()
9557 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_finish_page_flip() local
9559 do_intel_finish_page_flip(dev, crtc); in intel_finish_page_flip()
9565 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; in intel_finish_page_flip_plane() local
9567 do_intel_finish_page_flip(dev, crtc); in intel_finish_page_flip_plane()
9576 static bool page_flip_finished(struct intel_crtc *crtc) in page_flip_finished() argument
9578 struct drm_device *dev = crtc->base.dev; in page_flip_finished()
9582 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) in page_flip_finished()
9610 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == in page_flip_finished()
9611 crtc->unpin_work->gtt_offset && in page_flip_finished()
9612 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), in page_flip_finished()
9613 crtc->unpin_work->flip_count); in page_flip_finished()
9648 struct drm_crtc *crtc, in intel_gen2_queue_flip() argument
9654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen2_queue_flip()
9683 struct drm_crtc *crtc, in intel_gen3_queue_flip() argument
9689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen3_queue_flip()
9715 struct drm_crtc *crtc, in intel_gen4_queue_flip() argument
9722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen4_queue_flip()
9754 struct drm_crtc *crtc, in intel_gen6_queue_flip() argument
9761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen6_queue_flip()
9790 struct drm_crtc *crtc, in intel_gen7_queue_flip() argument
9796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen7_queue_flip()
9997 struct intel_crtc *crtc = in intel_mmio_flip_work_func() local
10001 mmio_flip = &crtc->mmio_flip; in intel_mmio_flip_work_func()
10004 crtc->reset_counter, in intel_mmio_flip_work_func()
10007 intel_do_mmio_flip(crtc); in intel_mmio_flip_work_func()
10009 mutex_lock(&crtc->base.dev->struct_mutex); in intel_mmio_flip_work_func()
10011 mutex_unlock(&crtc->base.dev->struct_mutex); in intel_mmio_flip_work_func()
10016 struct drm_crtc *crtc, in intel_queue_mmio_flip() argument
10022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_queue_mmio_flip()
10033 struct drm_crtc *crtc, in intel_default_queue_flip() argument
10043 struct drm_crtc *crtc) in __intel_pageflip_stall_check() argument
10046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __intel_pageflip_stall_check()
10061 work->flip_ready_vblank = drm_crtc_vblank_count(crtc); in __intel_pageflip_stall_check()
10064 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) in __intel_pageflip_stall_check()
10084 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_check_page_flip() local
10085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_check_page_flip()
10089 if (crtc == NULL) in intel_check_page_flip()
10093 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { in intel_check_page_flip()
10102 static int intel_crtc_page_flip(struct drm_crtc *crtc, in intel_crtc_page_flip() argument
10107 struct drm_device *dev = crtc->dev; in intel_crtc_page_flip()
10109 struct drm_framebuffer *old_fb = crtc->primary->fb; in intel_crtc_page_flip()
10111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_page_flip()
10112 struct drm_plane *primary = crtc->primary; in intel_crtc_page_flip()
10127 if (fb->pixel_format != crtc->primary->fb->pixel_format) in intel_crtc_page_flip()
10135 (fb->offsets[0] != crtc->primary->fb->offsets[0] || in intel_crtc_page_flip()
10136 fb->pitches[0] != crtc->primary->fb->pitches[0])) in intel_crtc_page_flip()
10147 work->crtc = crtc; in intel_crtc_page_flip()
10151 ret = drm_crtc_vblank_get(crtc); in intel_crtc_page_flip()
10161 if (__intel_pageflip_stall_check(dev, crtc)) { in intel_crtc_page_flip()
10168 drm_crtc_vblank_put(crtc); in intel_crtc_page_flip()
10183 crtc->primary->fb = fb; in intel_crtc_page_flip()
10184 update_state_fb(crtc->primary); in intel_crtc_page_flip()
10213 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, in intel_crtc_page_flip()
10214 crtc->primary->state, ring); in intel_crtc_page_flip()
10222 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, in intel_crtc_page_flip()
10230 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, in intel_crtc_page_flip()
10239 work->flip_queued_vblank = drm_crtc_vblank_count(crtc); in intel_crtc_page_flip()
10254 intel_unpin_fb_obj(fb, crtc->primary->state); in intel_crtc_page_flip()
10259 crtc->primary->fb = old_fb; in intel_crtc_page_flip()
10260 update_state_fb(crtc->primary); in intel_crtc_page_flip()
10269 drm_crtc_vblank_put(crtc); in intel_crtc_page_flip()
10300 struct intel_crtc *crtc; in intel_modeset_update_staged_output_state() local
10311 to_intel_crtc(encoder->base.crtc); in intel_modeset_update_staged_output_state()
10314 for_each_intel_crtc(dev, crtc) { in intel_modeset_update_staged_output_state()
10315 crtc->new_enabled = crtc->base.state->enable; in intel_modeset_update_staged_output_state()
10317 if (crtc->new_enabled) in intel_modeset_update_staged_output_state()
10318 crtc->new_config = crtc->config; in intel_modeset_update_staged_output_state()
10320 crtc->new_config = NULL; in intel_modeset_update_staged_output_state()
10336 connector->base.state->crtc = in intel_modeset_update_connector_atomic_state()
10337 connector->base.encoder->crtc; in intel_modeset_update_connector_atomic_state()
10340 connector->base.state->crtc = NULL; in intel_modeset_update_connector_atomic_state()
10352 struct intel_crtc *crtc; in intel_modeset_commit_output_state() local
10361 encoder->base.crtc = &encoder->new_crtc->base; in intel_modeset_commit_output_state()
10364 for_each_intel_crtc(dev, crtc) { in intel_modeset_commit_output_state()
10365 crtc->base.state->enable = crtc->new_enabled; in intel_modeset_commit_output_state()
10366 crtc->base.enabled = crtc->new_enabled; in intel_modeset_commit_output_state()
10409 compute_baseline_pipe_bpp(struct intel_crtc *crtc, in compute_baseline_pipe_bpp() argument
10413 struct drm_device *dev = crtc->base.dev; in compute_baseline_pipe_bpp()
10464 if (state->connector_states[i]->crtc != &crtc->base) in compute_baseline_pipe_bpp()
10484 static void intel_dump_pipe_config(struct intel_crtc *crtc, in intel_dump_pipe_config() argument
10488 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, in intel_dump_pipe_config()
10489 context, pipe_name(crtc->pipe)); in intel_dump_pipe_config()
10546 static bool check_single_encoder_cloning(struct intel_crtc *crtc, in check_single_encoder_cloning() argument
10549 struct drm_device *dev = crtc->base.dev; in check_single_encoder_cloning()
10553 if (source_encoder->new_crtc != crtc) in check_single_encoder_cloning()
10563 static bool check_encoder_cloning(struct intel_crtc *crtc) in check_encoder_cloning() argument
10565 struct drm_device *dev = crtc->base.dev; in check_encoder_cloning()
10569 if (encoder->new_crtc != crtc) in check_encoder_cloning()
10572 if (!check_single_encoder_cloning(crtc, encoder)) in check_encoder_cloning()
10632 intel_modeset_pipe_config(struct drm_crtc *crtc, in intel_modeset_pipe_config() argument
10637 struct drm_device *dev = crtc->dev; in intel_modeset_pipe_config()
10646 if (!check_encoder_cloning(to_intel_crtc(crtc))) { in intel_modeset_pipe_config()
10656 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); in intel_modeset_pipe_config()
10662 pipe_config->base.crtc = crtc; in intel_modeset_pipe_config()
10667 (enum transcoder) to_intel_crtc(crtc)->pipe; in intel_modeset_pipe_config()
10687 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), in intel_modeset_pipe_config()
10723 if (connector_state->crtc != crtc) in intel_modeset_pipe_config()
10740 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); in intel_modeset_pipe_config()
10769 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, in intel_modeset_affected_pipes() argument
10773 struct drm_device *dev = crtc->dev; in intel_modeset_affected_pipes()
10789 tmp_crtc = connector->base.encoder->crtc; in intel_modeset_affected_pipes()
10800 if (encoder->base.crtc == &encoder->new_crtc->base) in intel_modeset_affected_pipes()
10803 if (encoder->base.crtc) { in intel_modeset_affected_pipes()
10804 tmp_crtc = encoder->base.crtc; in intel_modeset_affected_pipes()
10826 intel_crtc = to_intel_crtc(crtc); in intel_modeset_affected_pipes()
10854 static bool intel_crtc_in_use(struct drm_crtc *crtc) in intel_crtc_in_use() argument
10857 struct drm_device *dev = crtc->dev; in intel_crtc_in_use()
10860 if (encoder->crtc == crtc) in intel_crtc_in_use()
10877 if (!intel_encoder->base.crtc) in intel_modeset_update_state()
10880 intel_crtc = to_intel_crtc(intel_encoder->base.crtc); in intel_modeset_update_state()
10897 if (!connector->encoder || !connector->encoder->crtc) in intel_modeset_update_state()
10900 intel_crtc = to_intel_crtc(connector->encoder->crtc); in intel_modeset_update_state()
11212 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, in check_encoder_state()
11214 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, in check_encoder_state()
11225 I915_STATE_WARN(!!encoder->base.crtc != enabled, in check_encoder_state()
11228 !!encoder->base.crtc, enabled); in check_encoder_state()
11229 I915_STATE_WARN(active && !encoder->base.crtc, in check_encoder_state()
11242 if (!encoder->base.crtc) in check_encoder_state()
11245 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; in check_encoder_state()
11258 struct intel_crtc *crtc; in check_crtc_state() local
11262 for_each_intel_crtc(dev, crtc) { in check_crtc_state()
11269 crtc->base.base.id); in check_crtc_state()
11271 I915_STATE_WARN(crtc->active && !crtc->base.state->enable, in check_crtc_state()
11275 if (encoder->base.crtc != &crtc->base) in check_crtc_state()
11282 I915_STATE_WARN(active != crtc->active, in check_crtc_state()
11284 "(expected %i, found %i)\n", active, crtc->active); in check_crtc_state()
11285 I915_STATE_WARN(enabled != crtc->base.state->enable, in check_crtc_state()
11288 crtc->base.state->enable); in check_crtc_state()
11290 active = dev_priv->display.get_pipe_config(crtc, in check_crtc_state()
11294 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in check_crtc_state()
11295 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in check_crtc_state()
11296 active = crtc->active; in check_crtc_state()
11300 if (encoder->base.crtc != &crtc->base) in check_crtc_state()
11306 I915_STATE_WARN(crtc->active != active, in check_crtc_state()
11308 "(expected %i, found %i)\n", crtc->active, active); in check_crtc_state()
11311 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { in check_crtc_state()
11313 intel_dump_pipe_config(crtc, &pipe_config, in check_crtc_state()
11315 intel_dump_pipe_config(crtc, crtc->config, in check_crtc_state()
11325 struct intel_crtc *crtc; in check_shared_dpll_state() local
11351 for_each_intel_crtc(dev, crtc) { in check_shared_dpll_state()
11352 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) in check_shared_dpll_state()
11354 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) in check_shared_dpll_state()
11392 static void update_scanline_offset(struct intel_crtc *crtc) in update_scanline_offset() argument
11394 struct drm_device *dev = crtc->base.dev; in update_scanline_offset()
11415 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; in update_scanline_offset()
11422 crtc->scanline_offset = vtotal - 1; in update_scanline_offset()
11424 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { in update_scanline_offset()
11425 crtc->scanline_offset = 2; in update_scanline_offset()
11427 crtc->scanline_offset = 1; in update_scanline_offset()
11431 intel_modeset_compute_config(struct drm_crtc *crtc, in intel_modeset_compute_config() argument
11439 struct drm_device *dev = crtc->dev; in intel_modeset_compute_config()
11444 ret = drm_atomic_add_affected_connectors(state, crtc); in intel_modeset_compute_config()
11448 intel_modeset_affected_pipes(crtc, modeset_pipes, in intel_modeset_compute_config()
11468 if (WARN_ON(&intel_crtc->base != crtc)) in intel_modeset_compute_config()
11471 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state); in intel_modeset_compute_config()
11475 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, in intel_modeset_compute_config()
11479 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; in intel_modeset_compute_config()
11512 static int __intel_set_mode(struct drm_crtc *crtc, in __intel_set_mode() argument
11520 struct drm_device *dev = crtc->dev; in __intel_set_mode()
11537 *saved_mode = crtc->mode; in __intel_set_mode()
11540 to_intel_crtc(crtc)->new_config = pipe_config; in __intel_set_mode()
11576 crtc->mode = *mode; in __intel_set_mode()
11579 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); in __intel_set_mode()
11586 drm_calc_timestamping_constants(crtc, in __intel_set_mode()
11620 if (ret && crtc->state->enable) in __intel_set_mode()
11621 crtc->mode = *saved_mode; in __intel_set_mode()
11624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __intel_set_mode()
11643 static int intel_set_mode_pipes(struct drm_crtc *crtc, in intel_set_mode_pipes() argument
11653 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, in intel_set_mode_pipes()
11657 intel_modeset_check_state(crtc->dev); in intel_set_mode_pipes()
11662 static int intel_set_mode(struct drm_crtc *crtc, in intel_set_mode() argument
11671 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state, in intel_set_mode()
11681 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, in intel_set_mode()
11691 void intel_crtc_restore_mode(struct drm_crtc *crtc) in intel_crtc_restore_mode() argument
11693 struct drm_device *dev = crtc->dev; in intel_crtc_restore_mode()
11702 crtc->base.id); in intel_crtc_restore_mode()
11714 if (&encoder->new_crtc->base != crtc) in intel_crtc_restore_mode()
11730 connector_state->crtc = crtc; in intel_crtc_restore_mode()
11735 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, in intel_crtc_restore_mode()
11757 struct drm_crtc *crtc; in intel_set_config_save_state() local
11785 for_each_crtc(dev, crtc) { in intel_set_config_save_state()
11786 config->save_crtc_enabled[count++] = crtc->state->enable; in intel_set_config_save_state()
11791 config->save_encoder_crtcs[count++] = encoder->crtc; in intel_set_config_save_state()
11805 struct intel_crtc *crtc; in intel_set_config_restore_state() local
11811 for_each_intel_crtc(dev, crtc) { in intel_set_config_restore_state()
11812 crtc->new_enabled = config->save_crtc_enabled[count++]; in intel_set_config_restore_state()
11814 if (crtc->new_enabled) in intel_set_config_restore_state()
11815 crtc->new_config = crtc->config; in intel_set_config_restore_state()
11817 crtc->new_config = NULL; in intel_set_config_restore_state()
11846 set->connectors[i]->encoder->crtc == set->crtc && in is_crtc_connector_off()
11862 } else if (set->crtc->primary->fb != set->fb) { in intel_set_config_compute_mode_changes()
11869 if (set->crtc->primary->fb == NULL) { in intel_set_config_compute_mode_changes()
11871 to_intel_crtc(set->crtc); in intel_set_config_compute_mode_changes()
11883 set->crtc->primary->fb->pixel_format) { in intel_set_config_compute_mode_changes()
11890 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) in intel_set_config_compute_mode_changes()
11893 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { in intel_set_config_compute_mode_changes()
11895 drm_mode_debug_printmodeline(&set->crtc->mode); in intel_set_config_compute_mode_changes()
11901 set->crtc->base.id, config->mode_changed, config->fb_changed); in intel_set_config_compute_mode_changes()
11913 struct intel_crtc *crtc; in intel_modeset_stage_output_state() local
11926 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); in intel_modeset_stage_output_state()
11936 connector->base.encoder->crtc == set->crtc) { in intel_modeset_stage_output_state()
11961 new_crtc = connector->new_encoder->base.crtc; in intel_modeset_stage_output_state()
11965 new_crtc = set->crtc; in intel_modeset_stage_output_state()
11980 connector_state->crtc = new_crtc; in intel_modeset_stage_output_state()
12006 if (&encoder->new_crtc->base != encoder->base.crtc) { in intel_modeset_stage_output_state()
12024 connector_state->crtc = NULL; in intel_modeset_stage_output_state()
12027 for_each_intel_crtc(dev, crtc) { in intel_modeset_stage_output_state()
12028 crtc->new_enabled = false; in intel_modeset_stage_output_state()
12031 if (encoder->new_crtc == crtc) { in intel_modeset_stage_output_state()
12032 crtc->new_enabled = true; in intel_modeset_stage_output_state()
12037 if (crtc->new_enabled != crtc->base.state->enable) { in intel_modeset_stage_output_state()
12039 crtc->base.base.id, in intel_modeset_stage_output_state()
12040 crtc->new_enabled ? "en" : "dis"); in intel_modeset_stage_output_state()
12044 if (crtc->new_enabled) in intel_modeset_stage_output_state()
12045 crtc->new_config = crtc->config; in intel_modeset_stage_output_state()
12047 crtc->new_config = NULL; in intel_modeset_stage_output_state()
12053 static void disable_crtc_nofb(struct intel_crtc *crtc) in disable_crtc_nofb() argument
12055 struct drm_device *dev = crtc->base.dev; in disable_crtc_nofb()
12060 pipe_name(crtc->pipe)); in disable_crtc_nofb()
12064 connector->new_encoder->new_crtc == crtc) in disable_crtc_nofb()
12069 if (encoder->new_crtc == crtc) in disable_crtc_nofb()
12073 crtc->new_enabled = false; in disable_crtc_nofb()
12074 crtc->new_config = NULL; in disable_crtc_nofb()
12088 BUG_ON(!set->crtc); in intel_crtc_set_config()
12089 BUG_ON(!set->crtc->helper_private); in intel_crtc_set_config()
12097 set->crtc->base.id, set->fb->base.id, in intel_crtc_set_config()
12100 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); in intel_crtc_set_config()
12103 dev = set->crtc->dev; in intel_crtc_set_config()
12114 save_set.crtc = set->crtc; in intel_crtc_set_config()
12115 save_set.mode = &set->crtc->mode; in intel_crtc_set_config()
12116 save_set.x = set->crtc->x; in intel_crtc_set_config()
12117 save_set.y = set->crtc->y; in intel_crtc_set_config()
12118 save_set.fb = set->crtc->primary->fb; in intel_crtc_set_config()
12138 pipe_config = intel_modeset_compute_config(set->crtc, set->mode, in intel_crtc_set_config()
12148 to_intel_crtc(set->crtc)->config->has_audio) in intel_crtc_set_config()
12159 intel_update_pipe_size(to_intel_crtc(set->crtc)); in intel_crtc_set_config()
12162 ret = intel_set_mode_pipes(set->crtc, set->mode, in intel_crtc_set_config()
12167 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); in intel_crtc_set_config()
12168 struct drm_plane *primary = set->crtc->primary; in intel_crtc_set_config()
12172 ret = primary->funcs->update_plane(primary, set->crtc, set->fb, in intel_crtc_set_config()
12183 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); in intel_crtc_set_config()
12195 intel_modeset_check_state(set->crtc->dev); in intel_crtc_set_config()
12200 set->crtc->base.id, ret); in intel_crtc_set_config()
12212 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) in intel_crtc_set_config()
12213 disable_crtc_nofb(to_intel_crtc(save_set.crtc)); in intel_crtc_set_config()
12217 intel_set_mode(save_set.crtc, save_set.mode, in intel_crtc_set_config()
12290 struct intel_crtc *crtc; in ibx_pch_dpll_disable() local
12293 for_each_intel_crtc(dev, crtc) { in ibx_pch_dpll_disable()
12294 if (intel_crtc_to_shared_dpll(crtc) == pll) in ibx_pch_dpll_disable()
12295 assert_pch_transcoder_disabled(dev_priv, crtc->pipe); in ibx_pch_dpll_disable()
12454 struct drm_crtc *crtc = state->base.crtc; in intel_check_primary_plane() local
12462 crtc = crtc ? crtc : plane->crtc; in intel_check_primary_plane()
12463 intel_crtc = to_intel_crtc(crtc); in intel_check_primary_plane()
12465 ret = drm_plane_helper_check_update(plane, crtc, fb, in intel_check_primary_plane()
12488 dev_priv->fbc.crtc == intel_crtc && in intel_check_primary_plane()
12529 struct drm_crtc *crtc = state->base.crtc; in intel_commit_primary_plane() local
12536 crtc = crtc ? crtc : plane->crtc; in intel_commit_primary_plane()
12537 intel_crtc = to_intel_crtc(crtc); in intel_commit_primary_plane()
12540 crtc->x = src->x1 >> 16; in intel_commit_primary_plane()
12541 crtc->y = src->y1 >> 16; in intel_commit_primary_plane()
12550 dev_priv->display.update_primary_plane(crtc, plane->fb, in intel_commit_primary_plane()
12551 crtc->x, crtc->y); in intel_commit_primary_plane()
12560 intel_disable_primary_hw_plane(plane, crtc); in intel_commit_primary_plane()
12565 static void intel_begin_crtc_commit(struct drm_crtc *crtc) in intel_begin_crtc_commit() argument
12567 struct drm_device *dev = crtc->dev; in intel_begin_crtc_commit()
12569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_begin_crtc_commit()
12599 intel_crtc_wait_for_pending_flips(crtc); in intel_begin_crtc_commit()
12608 intel_pre_disable_primary(crtc); in intel_begin_crtc_commit()
12611 intel_update_watermarks(crtc); in intel_begin_crtc_commit()
12622 static void intel_finish_crtc_commit(struct drm_crtc *crtc) in intel_finish_crtc_commit() argument
12624 struct drm_device *dev = crtc->dev; in intel_finish_crtc_commit()
12626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_finish_crtc_commit()
12647 intel_post_enable_primary(crtc); in intel_finish_crtc_commit()
12651 intel_update_sprite_watermarks(p, crtc, 0, 0, 0, in intel_finish_crtc_commit()
12745 struct drm_crtc *crtc = state->base.crtc; in intel_check_cursor_plane() local
12756 crtc = crtc ? crtc : plane->crtc; in intel_check_cursor_plane()
12757 intel_crtc = to_intel_crtc(crtc); in intel_check_cursor_plane()
12759 ret = drm_plane_helper_check_update(plane, crtc, fb, in intel_check_cursor_plane()
12806 struct drm_crtc *crtc = state->base.crtc; in intel_commit_cursor_plane() local
12812 crtc = crtc ? crtc : plane->crtc; in intel_commit_cursor_plane()
12813 intel_crtc = to_intel_crtc(crtc); in intel_commit_cursor_plane()
12816 crtc->cursor_x = state->base.crtc_x; in intel_commit_cursor_plane()
12817 crtc->cursor_y = state->base.crtc_y; in intel_commit_cursor_plane()
12834 intel_crtc_update_cursor(crtc, state->visible); in intel_commit_cursor_plane()
12901 crtc_state->base.crtc = &intel_crtc->base; in intel_crtc_init()
12966 if (!encoder || WARN_ON(!encoder->crtc)) in intel_get_pipe_from_connector()
12969 return to_intel_crtc(encoder->crtc)->pipe; in intel_get_pipe_from_connector()
12977 struct intel_crtc *crtc; in intel_get_pipe_from_crtc_id() local
12986 crtc = to_intel_crtc(drmmode_crtc); in intel_get_pipe_from_crtc_id()
12987 pipe_from_crtc_id->pipe = crtc->pipe; in intel_get_pipe_from_crtc_id()
13769 struct intel_crtc *crtc; in intel_modeset_init() local
13864 for_each_intel_crtc(dev, crtc) { in intel_modeset_init()
13865 if (!crtc->active) in intel_modeset_init()
13876 dev_priv->display.get_initial_plane_config(crtc, in intel_modeset_init()
13877 &crtc->plane_config); in intel_modeset_init()
13882 intel_find_initial_plane_obj(crtc, &crtc->plane_config); in intel_modeset_init()
13912 intel_check_plane_mapping(struct intel_crtc *crtc) in intel_check_plane_mapping() argument
13914 struct drm_device *dev = crtc->base.dev; in intel_check_plane_mapping()
13921 reg = DSPCNTR(!crtc->plane); in intel_check_plane_mapping()
13925 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) in intel_check_plane_mapping()
13931 static void intel_sanitize_crtc(struct intel_crtc *crtc) in intel_sanitize_crtc() argument
13933 struct drm_device *dev = crtc->base.dev; in intel_sanitize_crtc()
13938 reg = PIPECONF(crtc->config->cpu_transcoder); in intel_sanitize_crtc()
13942 drm_crtc_vblank_reset(&crtc->base); in intel_sanitize_crtc()
13943 if (crtc->active) { in intel_sanitize_crtc()
13944 update_scanline_offset(crtc); in intel_sanitize_crtc()
13945 drm_crtc_vblank_on(&crtc->base); in intel_sanitize_crtc()
13951 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { in intel_sanitize_crtc()
13956 crtc->base.base.id); in intel_sanitize_crtc()
13961 plane = crtc->plane; in intel_sanitize_crtc()
13962 crtc->plane = !plane; in intel_sanitize_crtc()
13963 crtc->primary_enabled = true; in intel_sanitize_crtc()
13964 dev_priv->display.crtc_disable(&crtc->base); in intel_sanitize_crtc()
13965 crtc->plane = plane; in intel_sanitize_crtc()
13969 if (connector->encoder->base.crtc != &crtc->base) in intel_sanitize_crtc()
13978 if (connector->encoder->base.crtc == &crtc->base) { in intel_sanitize_crtc()
13979 connector->encoder->base.crtc = NULL; in intel_sanitize_crtc()
13983 WARN_ON(crtc->active); in intel_sanitize_crtc()
13984 crtc->base.state->enable = false; in intel_sanitize_crtc()
13985 crtc->base.enabled = false; in intel_sanitize_crtc()
13989 crtc->pipe == PIPE_A && !crtc->active) { in intel_sanitize_crtc()
13999 intel_crtc_update_dpms(&crtc->base); in intel_sanitize_crtc()
14001 if (crtc->active != crtc->base.state->enable) { in intel_sanitize_crtc()
14008 crtc->base.base.id, in intel_sanitize_crtc()
14009 crtc->base.state->enable ? "enabled" : "disabled", in intel_sanitize_crtc()
14010 crtc->active ? "enabled" : "disabled"); in intel_sanitize_crtc()
14012 crtc->base.state->enable = crtc->active; in intel_sanitize_crtc()
14013 crtc->base.enabled = crtc->active; in intel_sanitize_crtc()
14020 WARN_ON(crtc->active); in intel_sanitize_crtc()
14022 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { in intel_sanitize_crtc()
14024 encoder->base.crtc = NULL; in intel_sanitize_crtc()
14028 if (crtc->active || HAS_GMCH_DISPLAY(dev)) { in intel_sanitize_crtc()
14042 crtc->cpu_fifo_underrun_disabled = true; in intel_sanitize_crtc()
14043 crtc->pch_fifo_underrun_disabled = true; in intel_sanitize_crtc()
14055 bool has_active_crtc = encoder->base.crtc && in intel_sanitize_encoder()
14056 to_intel_crtc(encoder->base.crtc)->active; in intel_sanitize_encoder()
14066 if (encoder->base.crtc) { in intel_sanitize_encoder()
14074 encoder->base.crtc = NULL; in intel_sanitize_encoder()
14120 static bool primary_get_hw_state(struct intel_crtc *crtc) in primary_get_hw_state() argument
14122 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in primary_get_hw_state()
14124 if (!crtc->active) in primary_get_hw_state()
14127 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; in primary_get_hw_state()
14134 struct intel_crtc *crtc; in intel_modeset_readout_hw_state() local
14139 for_each_intel_crtc(dev, crtc) { in intel_modeset_readout_hw_state()
14140 memset(crtc->config, 0, sizeof(*crtc->config)); in intel_modeset_readout_hw_state()
14142 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; in intel_modeset_readout_hw_state()
14144 crtc->active = dev_priv->display.get_pipe_config(crtc, in intel_modeset_readout_hw_state()
14145 crtc->config); in intel_modeset_readout_hw_state()
14147 crtc->base.state->enable = crtc->active; in intel_modeset_readout_hw_state()
14148 crtc->base.enabled = crtc->active; in intel_modeset_readout_hw_state()
14149 crtc->primary_enabled = primary_get_hw_state(crtc); in intel_modeset_readout_hw_state()
14152 crtc->base.base.id, in intel_modeset_readout_hw_state()
14153 crtc->active ? "enabled" : "disabled"); in intel_modeset_readout_hw_state()
14163 for_each_intel_crtc(dev, crtc) { in intel_modeset_readout_hw_state()
14164 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { in intel_modeset_readout_hw_state()
14166 pll->config.crtc_mask |= 1 << crtc->pipe; in intel_modeset_readout_hw_state()
14181 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_readout_hw_state()
14182 encoder->base.crtc = &crtc->base; in intel_modeset_readout_hw_state()
14183 encoder->get_config(encoder, crtc->config); in intel_modeset_readout_hw_state()
14185 encoder->base.crtc = NULL; in intel_modeset_readout_hw_state()
14192 encoder->base.crtc ? "enabled" : "disabled", in intel_modeset_readout_hw_state()
14219 struct intel_crtc *crtc; in intel_modeset_setup_hw_state() local
14230 for_each_intel_crtc(dev, crtc) { in intel_modeset_setup_hw_state()
14231 if (crtc->active && i915.fastboot) { in intel_modeset_setup_hw_state()
14232 intel_mode_from_pipe_config(&crtc->base.mode, in intel_modeset_setup_hw_state()
14233 crtc->config); in intel_modeset_setup_hw_state()
14235 crtc->base.base.id); in intel_modeset_setup_hw_state()
14236 drm_mode_debug_printmodeline(&crtc->base.mode); in intel_modeset_setup_hw_state()
14246 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
14247 intel_sanitize_crtc(crtc); in intel_modeset_setup_hw_state()
14248 intel_dump_pipe_config(crtc, crtc->config, in intel_modeset_setup_hw_state()
14279 struct drm_crtc *crtc = in intel_modeset_setup_hw_state() local
14282 intel_crtc_restore_mode(crtc); in intel_modeset_setup_hw_state()
14622 struct intel_crtc *crtc; in intel_modeset_preclose() local
14624 for_each_intel_crtc(dev, crtc) { in intel_modeset_preclose()
14629 work = crtc->unpin_work; in intel_modeset_preclose()