1860 	WARN_ON(!pll->config.crtc_mask);  in intel_prepare_shared_dpll()
1887 	if (WARN_ON(pll->config.crtc_mask == 0))  in intel_enable_shared_dpll()
1919 	if (WARN_ON(pll->config.crtc_mask == 0))  in intel_disable_shared_dpll()
4097 	if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {  in intel_put_shared_dpll()
4102 	pll->config.crtc_mask &= ~(1 << crtc->pipe);  in intel_put_shared_dpll()
4103 	if (pll->config.crtc_mask == 0) {  in intel_put_shared_dpll()
4126 		WARN_ON(pll->new_config->crtc_mask);  in intel_get_shared_dpll()
4135 		if (pll->new_config->crtc_mask == 0)  in intel_get_shared_dpll()
4143 				      pll->new_config->crtc_mask,  in intel_get_shared_dpll()
4152 		if (pll->new_config->crtc_mask == 0) {  in intel_get_shared_dpll()
4162 	if (pll->new_config->crtc_mask == 0)  in intel_get_shared_dpll()
4169 	pll->new_config->crtc_mask |= 1 << crtc->pipe;  in intel_get_shared_dpll()
4196 		pll->new_config->crtc_mask &= ~clear_pipes;  in intel_shared_dpll_start_config()
11340 		I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),  in check_shared_dpll_state()
11342 		     pll->active, hweight32(pll->config.crtc_mask));  in check_shared_dpll_state()
11360 		I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,  in check_shared_dpll_state()
11362 		     hweight32(pll->config.crtc_mask), enabled_crtcs);  in check_shared_dpll_state()
13186 		encoder->base.possible_crtcs = encoder->crtc_mask;  in intel_setup_outputs()
14162 		pll->config.crtc_mask = 0;  in intel_modeset_readout_hw_state()
14166 				pll->config.crtc_mask |= 1 << crtc->pipe;  in intel_modeset_readout_hw_state()
14171 			      pll->name, pll->config.crtc_mask, pll->on);  in intel_modeset_readout_hw_state()
14173 		if (pll->config.crtc_mask)  in intel_modeset_readout_hw_state()