Lines Matching refs:crtc_state
434 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, in intel_pipe_will_have_type() argument
437 struct drm_atomic_state *state = crtc_state->base.state; in intel_pipe_will_have_type()
447 if (connector_state->crtc != crtc_state->base.crtc) in intel_pipe_will_have_type()
463 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) in intel_ironlake_limit() argument
465 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_ironlake_limit()
468 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in intel_ironlake_limit()
487 intel_g4x_limit(struct intel_crtc_state *crtc_state) in intel_g4x_limit() argument
489 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_g4x_limit()
492 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in intel_g4x_limit()
497 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || in intel_g4x_limit()
498 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { in intel_g4x_limit()
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { in intel_g4x_limit()
509 intel_limit(struct intel_crtc_state *crtc_state, int refclk) in intel_limit() argument
511 struct drm_device *dev = crtc_state->base.crtc->dev; in intel_limit()
515 limit = intel_ironlake_limit(crtc_state, refclk); in intel_limit()
517 limit = intel_g4x_limit(crtc_state); in intel_limit()
519 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in intel_limit()
528 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in intel_limit()
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in intel_limit()
535 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) in intel_limit()
623 struct intel_crtc_state *crtc_state, in i9xx_find_best_dpll() argument
627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in i9xx_find_best_dpll()
632 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in i9xx_find_best_dpll()
686 struct intel_crtc_state *crtc_state, in pnv_find_best_dpll() argument
690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in pnv_find_best_dpll()
695 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in pnv_find_best_dpll()
747 struct intel_crtc_state *crtc_state, in g4x_find_best_dpll() argument
751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in g4x_find_best_dpll()
760 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in g4x_find_best_dpll()
846 struct intel_crtc_state *crtc_state, in vlv_find_best_dpll() argument
850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in vlv_find_best_dpll()
900 struct intel_crtc_state *crtc_state, in chv_find_best_dpll() argument
904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in chv_find_best_dpll()
4112 struct intel_crtc_state *crtc_state) in intel_get_shared_dpll() argument
4138 if (memcmp(&crtc_state->dpll_hw_state, in intel_get_shared_dpll()
4163 pll->new_config->hw_state = crtc_state->dpll_hw_state; in intel_get_shared_dpll()
4165 crtc_state->shared_dpll = i; in intel_get_shared_dpll()
6029 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, in i9xx_get_refclk() argument
6032 struct drm_device *dev = crtc_state->base.crtc->dev; in i9xx_get_refclk()
6036 WARN_ON(!crtc_state->base.state); in i9xx_get_refclk()
6040 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i9xx_get_refclk()
6064 struct intel_crtc_state *crtc_state, in i9xx_update_pll_dividers() argument
6071 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
6075 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
6080 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
6083 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i9xx_update_pll_dividers()
6085 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
6088 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
6474 struct intel_crtc_state *crtc_state, in i9xx_update_pll() argument
6482 struct dpll *clock = &crtc_state->dpll; in i9xx_update_pll()
6484 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); in i9xx_update_pll()
6486 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || in i9xx_update_pll()
6487 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); in i9xx_update_pll()
6491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) in i9xx_update_pll()
6497 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_update_pll()
6504 if (crtc_state->has_dp_encoder) in i9xx_update_pll()
6532 if (crtc_state->sdvo_tv_clock) in i9xx_update_pll()
6534 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i9xx_update_pll()
6541 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_update_pll()
6544 u32 dpll_md = (crtc_state->pixel_multiplier - 1) in i9xx_update_pll()
6546 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_update_pll()
6551 struct intel_crtc_state *crtc_state, in i8xx_update_pll() argument
6558 struct dpll *clock = &crtc_state->dpll; in i8xx_update_pll()
6560 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); in i8xx_update_pll()
6564 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { in i8xx_update_pll()
6575 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) in i8xx_update_pll()
6578 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && in i8xx_update_pll()
6585 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_update_pll()
6782 struct intel_crtc_state *crtc_state) in i9xx_crtc_compute_clock() argument
6792 struct drm_atomic_state *state = crtc_state->base.state; in i9xx_crtc_compute_clock()
6823 if (!crtc_state->clock_set) { in i9xx_crtc_compute_clock()
6824 refclk = i9xx_get_refclk(crtc_state, num_connectors); in i9xx_crtc_compute_clock()
6832 limit = intel_limit(crtc_state, refclk); in i9xx_crtc_compute_clock()
6833 ok = dev_priv->display.find_dpll(limit, crtc_state, in i9xx_crtc_compute_clock()
6834 crtc_state->port_clock, in i9xx_crtc_compute_clock()
6849 dev_priv->display.find_dpll(limit, crtc_state, in i9xx_crtc_compute_clock()
6855 crtc_state->dpll.n = clock.n; in i9xx_crtc_compute_clock()
6856 crtc_state->dpll.m1 = clock.m1; in i9xx_crtc_compute_clock()
6857 crtc_state->dpll.m2 = clock.m2; in i9xx_crtc_compute_clock()
6858 crtc_state->dpll.p1 = clock.p1; in i9xx_crtc_compute_clock()
6859 crtc_state->dpll.p2 = clock.p2; in i9xx_crtc_compute_clock()
6863 i8xx_update_pll(crtc, crtc_state, in i9xx_crtc_compute_clock()
6867 chv_update_pll(crtc, crtc_state); in i9xx_crtc_compute_clock()
6869 vlv_update_pll(crtc, crtc_state); in i9xx_crtc_compute_clock()
6871 i9xx_update_pll(crtc, crtc_state, in i9xx_crtc_compute_clock()
7479 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) in ironlake_get_refclk() argument
7481 struct drm_device *dev = crtc_state->base.crtc->dev; in ironlake_get_refclk()
7483 struct drm_atomic_state *state = crtc_state->base.state; in ironlake_get_refclk()
7494 if (connector_state->crtc != crtc_state->base.crtc) in ironlake_get_refclk()
7678 struct intel_crtc_state *crtc_state, in ironlake_compute_clocks() argument
7689 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); in ironlake_compute_clocks()
7691 refclk = ironlake_get_refclk(crtc_state); in ironlake_compute_clocks()
7698 limit = intel_limit(crtc_state, refclk); in ironlake_compute_clocks()
7699 ret = dev_priv->display.find_dpll(limit, crtc_state, in ironlake_compute_clocks()
7700 crtc_state->port_clock, in ironlake_compute_clocks()
7713 dev_priv->display.find_dpll(limit, crtc_state, in ironlake_compute_clocks()
7739 struct intel_crtc_state *crtc_state, in ironlake_compute_dpll() argument
7746 struct drm_atomic_state *state = crtc_state->base.state; in ironlake_compute_dpll()
7758 if (connector_state->crtc != crtc_state->base.crtc) in ironlake_compute_dpll()
7785 } else if (crtc_state->sdvo_tv_clock) in ironlake_compute_dpll()
7788 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ironlake_compute_dpll()
7801 dpll |= (crtc_state->pixel_multiplier - 1) in ironlake_compute_dpll()
7806 if (crtc_state->has_dp_encoder) in ironlake_compute_dpll()
7810 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
7812 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
7814 switch (crtc_state->dpll.p2) { in ironlake_compute_dpll()
7838 struct intel_crtc_state *crtc_state) in ironlake_crtc_compute_clock() argument
7852 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, in ironlake_crtc_compute_clock()
7854 if (!ok && !crtc_state->clock_set) { in ironlake_crtc_compute_clock()
7859 if (!crtc_state->clock_set) { in ironlake_crtc_compute_clock()
7860 crtc_state->dpll.n = clock.n; in ironlake_crtc_compute_clock()
7861 crtc_state->dpll.m1 = clock.m1; in ironlake_crtc_compute_clock()
7862 crtc_state->dpll.m2 = clock.m2; in ironlake_crtc_compute_clock()
7863 crtc_state->dpll.p1 = clock.p1; in ironlake_crtc_compute_clock()
7864 crtc_state->dpll.p2 = clock.p2; in ironlake_crtc_compute_clock()
7868 if (crtc_state->has_pch_encoder) { in ironlake_crtc_compute_clock()
7869 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ironlake_crtc_compute_clock()
7873 dpll = ironlake_compute_dpll(crtc, crtc_state, in ironlake_crtc_compute_clock()
7877 crtc_state->dpll_hw_state.dpll = dpll; in ironlake_crtc_compute_clock()
7878 crtc_state->dpll_hw_state.fp0 = fp; in ironlake_crtc_compute_clock()
7880 crtc_state->dpll_hw_state.fp1 = fp2; in ironlake_crtc_compute_clock()
7882 crtc_state->dpll_hw_state.fp1 = fp; in ironlake_crtc_compute_clock()
7884 pll = intel_get_shared_dpll(crtc, crtc_state); in ironlake_crtc_compute_clock()
8474 struct intel_crtc_state *crtc_state) in haswell_crtc_compute_clock() argument
8476 if (!intel_ddi_pll_select(crtc, crtc_state)) in haswell_crtc_compute_clock()
9468 struct intel_crtc_state *crtc_state) in intel_crtc_set_state() argument
9471 crtc->config = crtc_state; in intel_crtc_set_state()
9472 crtc->base.state = &crtc_state->base; in intel_crtc_set_state()
10621 clear_intel_crtc_state(struct intel_crtc_state *crtc_state) in clear_intel_crtc_state() argument
10626 tmp_state = crtc_state->base; in clear_intel_crtc_state()
10627 memset(crtc_state, 0, sizeof *crtc_state); in clear_intel_crtc_state()
10628 crtc_state->base = tmp_state; in clear_intel_crtc_state()
12888 struct intel_crtc_state *crtc_state = NULL; in intel_crtc_init() local
12897 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_init()
12898 if (!crtc_state) in intel_crtc_init()
12900 intel_crtc_set_state(intel_crtc, crtc_state); in intel_crtc_init()
12901 crtc_state->base.crtc = &intel_crtc->base; in intel_crtc_init()
12955 kfree(crtc_state); in intel_crtc_init()