Lines Matching refs:dpll
554 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
556 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
1589 u32 dpll = pipe_config->dpll_hw_state.dpll; in vlv_enable_pll() local
1600 I915_WRITE(reg, dpll); in vlv_enable_pll()
1611 I915_WRITE(reg, dpll); in vlv_enable_pll()
1614 I915_WRITE(reg, dpll); in vlv_enable_pll()
1617 I915_WRITE(reg, dpll); in vlv_enable_pll()
1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1678 u32 dpll = crtc->config->dpll_hw_state.dpll; in i9xx_enable_pll() local
1697 dpll |= DPLL_DVO_2X_MODE; in i9xx_enable_pll()
1702 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1717 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1721 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1724 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1727 I915_WRITE(reg, dpll); in i9xx_enable_pll()
6053 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) in pnv_dpll_compute_fp() argument
6055 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
6058 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) in i9xx_dpll_compute_fp() argument
6060 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
6071 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
6075 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
6196 u32 dpll, dpll_md; in vlv_update_pll() local
6203 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | in vlv_update_pll()
6207 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_update_pll()
6208 dpll |= DPLL_VCO_ENABLE; in vlv_update_pll()
6209 pipe_config->dpll_hw_state.dpll = dpll; in vlv_update_pll()
6228 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
6229 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
6230 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
6231 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
6232 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
6310 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | in chv_update_pll()
6314 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_update_pll()
6333 bestn = pipe_config->dpll.n; in chv_prepare_pll()
6334 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
6335 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
6336 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
6337 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
6338 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
6339 vco = pipe_config->dpll.vco; in chv_prepare_pll()
6347 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
6436 const struct dpll *dpll) in vlv_force_pll_on() argument
6443 .dpll = *dpll, in vlv_force_pll_on()
6480 u32 dpll; in i9xx_update_pll() local
6482 struct dpll *clock = &crtc_state->dpll; in i9xx_update_pll()
6489 dpll = DPLL_VGA_MODE_DIS; in i9xx_update_pll()
6492 dpll |= DPLLB_MODE_LVDS; in i9xx_update_pll()
6494 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_update_pll()
6497 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_update_pll()
6502 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_update_pll()
6505 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_update_pll()
6509 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_update_pll()
6511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_update_pll()
6513 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_update_pll()
6517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_update_pll()
6520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_update_pll()
6523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_update_pll()
6526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_update_pll()
6530 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_update_pll()
6533 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_update_pll()
6536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_update_pll()
6538 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_update_pll()
6540 dpll |= DPLL_VCO_ENABLE; in i9xx_update_pll()
6541 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_update_pll()
6557 u32 dpll; in i8xx_update_pll() local
6558 struct dpll *clock = &crtc_state->dpll; in i8xx_update_pll()
6562 dpll = DPLL_VGA_MODE_DIS; in i8xx_update_pll()
6565 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_update_pll()
6568 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_update_pll()
6570 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_update_pll()
6572 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_update_pll()
6576 dpll |= DPLL_DVO_2X_MODE; in i8xx_update_pll()
6580 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_update_pll()
6582 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_update_pll()
6584 dpll |= DPLL_VCO_ENABLE; in i8xx_update_pll()
6585 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_update_pll()
6855 crtc_state->dpll.n = clock.n; in i9xx_crtc_compute_clock()
6856 crtc_state->dpll.m1 = clock.m1; in i9xx_crtc_compute_clock()
6857 crtc_state->dpll.m2 = clock.m2; in i9xx_crtc_compute_clock()
6858 crtc_state->dpll.p1 = clock.p1; in i9xx_crtc_compute_clock()
6859 crtc_state->dpll.p2 = clock.p2; in i9xx_crtc_compute_clock()
6920 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) in vlv_crtc_clock_get()
7099 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7107 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; in i9xx_get_pipe_config()
7113 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
7733 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) in ironlake_needs_fb_cb_tune() argument
7735 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; in ironlake_needs_fb_cb_tune()
7749 uint32_t dpll; in ironlake_compute_dpll() local
7788 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ironlake_compute_dpll()
7794 dpll = 0; in ironlake_compute_dpll()
7797 dpll |= DPLLB_MODE_LVDS; in ironlake_compute_dpll()
7799 dpll |= DPLLB_MODE_DAC_SERIAL; in ironlake_compute_dpll()
7801 dpll |= (crtc_state->pixel_multiplier - 1) in ironlake_compute_dpll()
7805 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
7807 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
7810 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
7812 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
7814 switch (crtc_state->dpll.p2) { in ironlake_compute_dpll()
7816 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ironlake_compute_dpll()
7819 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ironlake_compute_dpll()
7822 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ironlake_compute_dpll()
7825 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ironlake_compute_dpll()
7830 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ironlake_compute_dpll()
7832 dpll |= PLL_REF_INPUT_DREFCLK; in ironlake_compute_dpll()
7834 return dpll | DPLL_VCO_ENABLE; in ironlake_compute_dpll()
7842 u32 dpll = 0, fp = 0, fp2 = 0; in ironlake_crtc_compute_clock() local
7860 crtc_state->dpll.n = clock.n; in ironlake_crtc_compute_clock()
7861 crtc_state->dpll.m1 = clock.m1; in ironlake_crtc_compute_clock()
7862 crtc_state->dpll.m2 = clock.m2; in ironlake_crtc_compute_clock()
7863 crtc_state->dpll.p1 = clock.p1; in ironlake_crtc_compute_clock()
7864 crtc_state->dpll.p2 = clock.p2; in ironlake_crtc_compute_clock()
7869 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ironlake_crtc_compute_clock()
7873 dpll = ironlake_compute_dpll(crtc, crtc_state, in ironlake_crtc_compute_clock()
7877 crtc_state->dpll_hw_state.dpll = dpll; in ironlake_crtc_compute_clock()
8234 tmp = pipe_config->dpll_hw_state.dpll; in ironlake_get_pipe_config()
9207 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk() local
9209 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
9226 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get() local
9231 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in i9xx_crtc_clock_get()
9247 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
9250 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
9253 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
9255 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
9259 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
9264 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
9277 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
9285 if (dpll & PLL_P1_DIVIDE_BY_TWO) in i9xx_crtc_clock_get()
9288 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
9291 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
9374 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); in intel_crtc_mode_get()
9413 int dpll; in intel_decrease_pllclock() local
9419 dpll = I915_READ(dpll_reg); in intel_decrease_pllclock()
9420 dpll |= DISPLAY_RATE_SELECT_FPA1; in intel_decrease_pllclock()
9421 I915_WRITE(dpll_reg, dpll); in intel_decrease_pllclock()
9423 dpll = I915_READ(dpll_reg); in intel_decrease_pllclock()
9424 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) in intel_decrease_pllclock()
11107 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); in intel_pipe_config_compare()
12250 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
12270 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); in ibx_pch_dpll_enable()
12281 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); in ibx_pch_dpll_enable()