5858 		adjusted_mode->hsync_start == adjusted_mode->hdisplay)  in intel_crtc_compute_config()
6696 	pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;  in intel_get_pipe_timings()
6702 	mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;  in intel_mode_from_pipe_config()
8921 	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);  in intel_framebuffer_size_for_mode()
8938 	mode_cmd.width = mode->hdisplay;  in intel_framebuffer_create_for_mode()
8966 	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,  in mode_fits_in_fbdev()
9380 	mode->hdisplay = (htot & 0xffff) + 1;  in intel_crtc_mode_get()
11601 		int vdisplay, hdisplay;  in __intel_set_mode()  local
11603 		drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);  in __intel_set_mode()
11606 						   hdisplay, vdisplay,  in __intel_set_mode()
11608 						   hdisplay << 16, vdisplay << 16);  in __intel_set_mode()
12169 		int vdisplay, hdisplay;  in intel_crtc_set_config()  local
12171 		drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);  in intel_crtc_set_config()
12173 						   0, 0, hdisplay, vdisplay,  in intel_crtc_set_config()
12175 						   hdisplay << 16, vdisplay << 16);  in intel_crtc_set_config()