126 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;  member
158 	.p1 = { .min = 2, .max = 33 },
171 	.p1 = { .min = 2, .max = 33 },
184 	.p1 = { .min = 1, .max = 6 },
197 	.p1 = { .min = 1, .max = 8 },
210 	.p1 = { .min = 1, .max = 8 },
224 	.p1 = { .min = 1, .max = 3},
239 	.p1 = { .min = 1, .max = 8},
252 	.p1 = { .min = 2, .max = 8 },
266 	.p1 = { .min = 2, .max = 6 },
282 	.p1 = { .min = 1, .max = 8 },
295 	.p1 = { .min = 1, .max = 8 },
313 	.p1 = { .min = 1, .max = 8 },
326 	.p1 = { .min = 2, .max = 8 },
339 	.p1 = { .min = 2, .max = 8 },
353 	.p1 = { .min = 2, .max = 8 },
366 	.p1 = { .min = 2, .max = 6 },
383 	.p1 = { .min = 2, .max = 3 },
399 	.p1 = { .min = 2, .max = 4 },
406 	clock->p = clock->p1 * clock->p2;  in vlv_clock()
547 	clock->p = clock->p1 * clock->p2;  in pineview_clock()
562 	clock->p = clock->p1 * clock->p2;  in i9xx_clock()
572 	clock->p = clock->p1 * clock->p2;  in chv_clock()
592 	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)  in intel_PLL_is_valid()
659 				for (clock.p1 = limit->p1.min;  in i9xx_find_best_dpll()
660 					clock.p1 <= limit->p1.max; clock.p1++) {  in i9xx_find_best_dpll()
720 				for (clock.p1 = limit->p1.min;  in pnv_find_best_dpll()
721 					clock.p1 <= limit->p1.max; clock.p1++) {  in pnv_find_best_dpll()
781 				for (clock.p1 = limit->p1.max;  in g4x_find_best_dpll()
782 				     clock.p1 >= limit->p1.min; clock.p1--) {  in g4x_find_best_dpll()
864 		for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {  in vlv_find_best_dpll()
867 				clock.p = clock.p1 * clock.p2;  in vlv_find_best_dpll()
922 	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {  in chv_find_best_dpll()
928 			clock.p = clock.p1 * clock.p2;  in chv_find_best_dpll()
6231 	bestp1 = pipe_config->dpll.p1;  in vlv_prepare_pll()
6337 	bestp1 = pipe_config->dpll.p1;  in chv_prepare_pll()
6509 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;  in i9xx_update_pll()
6511 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i9xx_update_pll()
6513 			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;  in i9xx_update_pll()
6565 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i8xx_update_pll()
6567 		if (clock->p1 == 2)  in i8xx_update_pll()
6570 			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i8xx_update_pll()
6858 		crtc_state->dpll.p1 = clock.p1;  in i9xx_crtc_compute_clock()
6930 	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;  in vlv_crtc_clock_get()
7029 	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;  in chv_crtc_clock_get()
7810 	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in ironlake_compute_dpll()
7812 	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;  in ironlake_compute_dpll()
7863 		crtc_state->dpll.p1 = clock.p1;  in ironlake_crtc_compute_clock()
9247 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>  in i9xx_crtc_clock_get()
9250 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>  in i9xx_crtc_clock_get()
9277 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>  in i9xx_crtc_clock_get()
9286 				clock.p1 = 2;  in i9xx_crtc_clock_get()
9288 				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>  in i9xx_crtc_clock_get()