Lines Matching refs:plane
1321 enum plane plane, bool state) in assert_plane() argument
1327 reg = DSPCNTR(plane); in assert_plane()
1332 plane_name(plane), state_string(state), state_string(cur_state)); in assert_plane()
2189 enum plane plane) in intel_flush_primary_plane() argument
2192 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); in intel_flush_primary_plane()
2205 static void intel_enable_primary_hw_plane(struct drm_plane *plane, in intel_enable_primary_hw_plane() argument
2208 struct drm_device *dev = plane->dev; in intel_enable_primary_hw_plane()
2220 dev_priv->display.update_primary_plane(crtc, plane->fb, in intel_enable_primary_hw_plane()
2239 static void intel_disable_primary_hw_plane(struct drm_plane *plane, in intel_disable_primary_hw_plane() argument
2242 struct drm_device *dev = plane->dev; in intel_disable_primary_hw_plane()
2254 dev_priv->display.update_primary_plane(crtc, plane->fb, in intel_disable_primary_hw_plane()
2354 intel_pin_and_fence_fb_obj(struct drm_plane *plane, in intel_pin_and_fence_fb_obj() argument
2593 update_state_fb(struct drm_plane *plane) in update_state_fb() argument
2595 if (plane->fb == plane->state->fb) in update_state_fb()
2598 if (plane->state->fb) in update_state_fb()
2599 drm_framebuffer_unreference(plane->state->fb); in update_state_fb()
2600 plane->state->fb = plane->fb; in update_state_fb()
2601 if (plane->state->fb) in update_state_fb()
2602 drm_framebuffer_reference(plane->state->fb); in update_state_fb()
2673 int plane = intel_crtc->plane; in i9xx_update_primary_plane() local
2676 u32 reg = DSPCNTR(plane); in i9xx_update_primary_plane()
2682 I915_WRITE(DSPSURF(plane), 0); in i9xx_update_primary_plane()
2684 I915_WRITE(DSPADDR(plane), 0); in i9xx_update_primary_plane()
2706 I915_WRITE(DSPSIZE(plane), in i9xx_update_primary_plane()
2709 I915_WRITE(DSPPOS(plane), 0); in i9xx_update_primary_plane()
2710 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { in i9xx_update_primary_plane()
2711 I915_WRITE(PRIMSIZE(plane), in i9xx_update_primary_plane()
2714 I915_WRITE(PRIMPOS(plane), 0); in i9xx_update_primary_plane()
2715 I915_WRITE(PRIMCNSTALPHA(plane), 0); in i9xx_update_primary_plane()
2783 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); in i9xx_update_primary_plane()
2785 I915_WRITE(DSPSURF(plane), in i9xx_update_primary_plane()
2787 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); in i9xx_update_primary_plane()
2788 I915_WRITE(DSPLINOFF(plane), linear_offset); in i9xx_update_primary_plane()
2790 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); in i9xx_update_primary_plane()
2802 int plane = intel_crtc->plane; in ironlake_update_primary_plane() local
2805 u32 reg = DSPCNTR(plane); in ironlake_update_primary_plane()
2810 I915_WRITE(DSPSURF(plane), 0); in ironlake_update_primary_plane()
2884 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); in ironlake_update_primary_plane()
2885 I915_WRITE(DSPSURF(plane), in ironlake_update_primary_plane()
2888 I915_WRITE(DSPOFFSET(plane), (y << 16) | x); in ironlake_update_primary_plane()
2890 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); in ironlake_update_primary_plane()
2891 I915_WRITE(DSPLINOFF(plane), linear_offset); in ironlake_update_primary_plane()
3054 enum plane plane = intel_crtc->plane; in intel_complete_page_flips() local
3056 intel_prepare_page_flip(dev, plane); in intel_complete_page_flips()
3057 intel_finish_page_flip_plane(dev, plane); in intel_complete_page_flips()
3790 trace_i915_flip_complete(intel_crtc->plane, in page_flip_completed()
4294 struct drm_plane *plane; in intel_enable_sprite_planes() local
4297 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { in intel_enable_sprite_planes()
4298 intel_plane = to_intel_plane(plane); in intel_enable_sprite_planes()
4309 static void disable_plane_internal(struct drm_plane *plane) in disable_plane_internal() argument
4311 struct intel_plane *intel_plane = to_intel_plane(plane); in disable_plane_internal()
4313 plane->funcs->atomic_duplicate_state(plane); in disable_plane_internal()
4317 intel_plane->commit_plane(plane, intel_state); in disable_plane_internal()
4319 intel_plane_destroy_state(plane, state); in disable_plane_internal()
4326 struct drm_plane *plane; in intel_disable_sprite_planes() local
4329 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { in intel_disable_sprite_planes()
4330 intel_plane = to_intel_plane(plane); in intel_disable_sprite_planes()
4331 if (plane->fb && intel_plane->pipe == pipe) in intel_disable_sprite_planes()
4332 disable_plane_internal(plane); in intel_disable_sprite_planes()
4347 assert_plane_enabled(dev_priv, crtc->plane); in hsw_enable_ips()
4377 assert_plane_enabled(dev_priv, crtc->plane); in hsw_disable_ips()
6946 int pipe = crtc->pipe, plane = crtc->plane; in i9xx_get_initial_plane_config() local
6952 val = I915_READ(DSPCNTR(plane)); in i9xx_get_initial_plane_config()
6978 offset = I915_READ(DSPTILEOFF(plane)); in i9xx_get_initial_plane_config()
6980 offset = I915_READ(DSPLINOFF(plane)); in i9xx_get_initial_plane_config()
6981 base = I915_READ(DSPSURF(plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
6983 base = I915_READ(DSPADDR(plane)); in i9xx_get_initial_plane_config()
7001 pipe_name(pipe), plane, fb->width, fb->height, in i9xx_get_initial_plane_config()
9562 void intel_finish_page_flip_plane(struct drm_device *dev, int plane) in intel_finish_page_flip_plane() argument
9565 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; in intel_finish_page_flip_plane()
9610 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == in page_flip_finished()
9616 void intel_prepare_page_flip(struct drm_device *dev, int plane) in intel_prepare_page_flip() argument
9620 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); in intel_prepare_page_flip()
9665 if (intel_crtc->plane) in intel_gen2_queue_flip()
9672 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen2_queue_flip()
9697 if (intel_crtc->plane) in intel_gen3_queue_flip()
9704 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen3_queue_flip()
9735 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen4_queue_flip()
9770 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen6_queue_flip()
9800 switch (intel_crtc->plane) { in intel_gen7_queue_flip()
9955 reg = DSPCNTR(intel_crtc->plane); in ilk_do_mmio_flip()
9965 I915_WRITE(DSPSURF(intel_crtc->plane), in ilk_do_mmio_flip()
9967 POSTING_READ(DSPSURF(intel_crtc->plane)); in ilk_do_mmio_flip()
10070 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); in __intel_pageflip_stall_check()
10072 addr = I915_READ(DSPADDR(intel_crtc->plane)); in __intel_pageflip_stall_check()
10249 trace_i915_flip_request(intel_crtc->plane, obj); in intel_crtc_page_flip()
11137 int plane; in check_wm_state() local
11153 for_each_plane(dev_priv, pipe, plane) { in check_wm_state()
11154 hw_entry = &hw_ddb.plane[pipe][plane]; in check_wm_state()
11155 sw_entry = &sw_ddb->plane[pipe][plane]; in check_wm_state()
11162 pipe_name(pipe), plane + 1, in check_wm_state()
12350 bool intel_wm_need_update(struct drm_plane *plane, in intel_wm_need_update() argument
12354 if (!plane->state->fb || !state->fb || in intel_wm_need_update()
12355 plane->state->fb->modifier[0] != state->fb->modifier[0] || in intel_wm_need_update()
12356 plane->state->rotation != state->rotation) in intel_wm_need_update()
12375 intel_prepare_plane_fb(struct drm_plane *plane, in intel_prepare_plane_fb() argument
12379 struct drm_device *dev = plane->dev; in intel_prepare_plane_fb()
12380 struct intel_plane *intel_plane = to_intel_plane(plane); in intel_prepare_plane_fb()
12383 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); in intel_prepare_plane_fb()
12390 switch (plane->type) { in intel_prepare_plane_fb()
12404 if (plane->type == DRM_PLANE_TYPE_CURSOR && in intel_prepare_plane_fb()
12411 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); in intel_prepare_plane_fb()
12430 intel_cleanup_plane_fb(struct drm_plane *plane, in intel_cleanup_plane_fb() argument
12434 struct drm_device *dev = plane->dev; in intel_cleanup_plane_fb()
12440 if (plane->type != DRM_PLANE_TYPE_CURSOR || in intel_cleanup_plane_fb()
12449 intel_check_primary_plane(struct drm_plane *plane, in intel_check_primary_plane() argument
12452 struct drm_device *dev = plane->dev; in intel_check_primary_plane()
12462 crtc = crtc ? crtc : plane->crtc; in intel_check_primary_plane()
12465 ret = drm_plane_helper_check_update(plane, crtc, fb, in intel_check_primary_plane()
12518 if (intel_wm_need_update(plane, &state->base)) in intel_check_primary_plane()
12526 intel_commit_primary_plane(struct drm_plane *plane, in intel_commit_primary_plane() argument
12531 struct drm_device *dev = plane->dev; in intel_commit_primary_plane()
12536 crtc = crtc ? crtc : plane->crtc; in intel_commit_primary_plane()
12539 plane->fb = fb; in intel_commit_primary_plane()
12550 dev_priv->display.update_primary_plane(crtc, plane->fb, in intel_commit_primary_plane()
12560 intel_disable_primary_hw_plane(plane, crtc); in intel_commit_primary_plane()
12664 void intel_plane_destroy(struct drm_plane *plane) in intel_plane_destroy() argument
12666 struct intel_plane *intel_plane = to_intel_plane(plane); in intel_plane_destroy()
12667 drm_plane_cleanup(plane); in intel_plane_destroy()
12705 primary->plane = pipe; in intel_primary_plane_create()
12709 primary->plane = !pipe; in intel_primary_plane_create()
12742 intel_check_cursor_plane(struct drm_plane *plane, in intel_check_cursor_plane() argument
12746 struct drm_device *dev = plane->dev; in intel_check_cursor_plane()
12756 crtc = crtc ? crtc : plane->crtc; in intel_check_cursor_plane()
12759 ret = drm_plane_helper_check_update(plane, crtc, fb, in intel_check_cursor_plane()
12792 if (plane->state->crtc_w != state->base.crtc_w) in intel_check_cursor_plane()
12803 intel_commit_cursor_plane(struct drm_plane *plane, in intel_commit_cursor_plane() argument
12807 struct drm_device *dev = plane->dev; in intel_commit_cursor_plane()
12812 crtc = crtc ? crtc : plane->crtc; in intel_commit_cursor_plane()
12815 plane->fb = state->base.fb; in intel_commit_cursor_plane()
12857 cursor->plane = pipe; in intel_cursor_plane_create()
12928 intel_crtc->plane = pipe; in intel_crtc_init()
12931 intel_crtc->plane = !pipe; in intel_crtc_init()
12939 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); in intel_crtc_init()
12940 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; in intel_crtc_init()
13921 reg = DSPCNTR(!crtc->plane); in intel_check_plane_mapping()
13953 bool plane; in intel_sanitize_crtc() local
13961 plane = crtc->plane; in intel_sanitize_crtc()
13962 crtc->plane = !plane; in intel_sanitize_crtc()
13965 crtc->plane = plane; in intel_sanitize_crtc()
14127 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; in primary_get_hw_state()
14464 } plane[I915_MAX_PIPES]; member
14515 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()
14516 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); in intel_display_capture_error_state()
14518 error->plane[i].size = I915_READ(DSPSIZE(i)); in intel_display_capture_error_state()
14519 error->plane[i].pos = I915_READ(DSPPOS(i)); in intel_display_capture_error_state()
14522 error->plane[i].addr = I915_READ(DSPADDR(i)); in intel_display_capture_error_state()
14524 error->plane[i].surface = I915_READ(DSPSURF(i)); in intel_display_capture_error_state()
14525 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); in intel_display_capture_error_state()
14586 err_printf(m, " CNTR: %08x\n", error->plane[i].control); in intel_display_print_error_state()
14587 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); in intel_display_print_error_state()
14589 err_printf(m, " SIZE: %08x\n", error->plane[i].size); in intel_display_print_error_state()
14590 err_printf(m, " POS: %08x\n", error->plane[i].pos); in intel_display_print_error_state()
14593 err_printf(m, " ADDR: %08x\n", error->plane[i].addr); in intel_display_print_error_state()
14595 err_printf(m, " SURF: %08x\n", error->plane[i].surface); in intel_display_print_error_state()
14596 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); in intel_display_print_error_state()