Lines Matching refs:pll
1139 struct intel_shared_dpll *pll, in assert_shared_dpll() argument
1145 if (WARN (!pll, in assert_shared_dpll()
1149 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); in assert_shared_dpll()
1152 pll->name, state_string(state), state_string(cur_state)); in assert_shared_dpll()
1855 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_prepare_shared_dpll() local
1857 if (WARN_ON(pll == NULL)) in intel_prepare_shared_dpll()
1860 WARN_ON(!pll->config.crtc_mask); in intel_prepare_shared_dpll()
1861 if (pll->active == 0) { in intel_prepare_shared_dpll()
1862 DRM_DEBUG_DRIVER("setting up %s\n", pll->name); in intel_prepare_shared_dpll()
1863 WARN_ON(pll->on); in intel_prepare_shared_dpll()
1864 assert_shared_dpll_disabled(dev_priv, pll); in intel_prepare_shared_dpll()
1866 pll->mode_set(dev_priv, pll); in intel_prepare_shared_dpll()
1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_enable_shared_dpll() local
1884 if (WARN_ON(pll == NULL)) in intel_enable_shared_dpll()
1887 if (WARN_ON(pll->config.crtc_mask == 0)) in intel_enable_shared_dpll()
1891 pll->name, pll->active, pll->on, in intel_enable_shared_dpll()
1894 if (pll->active++) { in intel_enable_shared_dpll()
1895 WARN_ON(!pll->on); in intel_enable_shared_dpll()
1896 assert_shared_dpll_enabled(dev_priv, pll); in intel_enable_shared_dpll()
1899 WARN_ON(pll->on); in intel_enable_shared_dpll()
1903 DRM_DEBUG_KMS("enabling %s\n", pll->name); in intel_enable_shared_dpll()
1904 pll->enable(dev_priv, pll); in intel_enable_shared_dpll()
1905 pll->on = true; in intel_enable_shared_dpll()
1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_disable_shared_dpll() local
1916 if (WARN_ON(pll == NULL)) in intel_disable_shared_dpll()
1919 if (WARN_ON(pll->config.crtc_mask == 0)) in intel_disable_shared_dpll()
1923 pll->name, pll->active, pll->on, in intel_disable_shared_dpll()
1926 if (WARN_ON(pll->active == 0)) { in intel_disable_shared_dpll()
1927 assert_shared_dpll_disabled(dev_priv, pll); in intel_disable_shared_dpll()
1931 assert_shared_dpll_enabled(dev_priv, pll); in intel_disable_shared_dpll()
1932 WARN_ON(!pll->on); in intel_disable_shared_dpll()
1933 if (--pll->active) in intel_disable_shared_dpll()
1936 DRM_DEBUG_KMS("disabling %s\n", pll->name); in intel_disable_shared_dpll()
1937 pll->disable(dev_priv, pll); in intel_disable_shared_dpll()
1938 pll->on = false; in intel_disable_shared_dpll()
4092 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_put_shared_dpll() local
4094 if (pll == NULL) in intel_put_shared_dpll()
4097 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { in intel_put_shared_dpll()
4098 WARN(1, "bad %s crtc mask\n", pll->name); in intel_put_shared_dpll()
4102 pll->config.crtc_mask &= ~(1 << crtc->pipe); in intel_put_shared_dpll()
4103 if (pll->config.crtc_mask == 0) { in intel_put_shared_dpll()
4104 WARN_ON(pll->on); in intel_put_shared_dpll()
4105 WARN_ON(pll->active); in intel_put_shared_dpll()
4115 struct intel_shared_dpll *pll; in intel_get_shared_dpll() local
4121 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4124 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4126 WARN_ON(pll->new_config->crtc_mask); in intel_get_shared_dpll()
4132 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4135 if (pll->new_config->crtc_mask == 0) in intel_get_shared_dpll()
4139 &pll->new_config->hw_state, in intel_get_shared_dpll()
4140 sizeof(pll->new_config->hw_state)) == 0) { in intel_get_shared_dpll()
4142 crtc->base.base.id, pll->name, in intel_get_shared_dpll()
4143 pll->new_config->crtc_mask, in intel_get_shared_dpll()
4144 pll->active); in intel_get_shared_dpll()
4151 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4152 if (pll->new_config->crtc_mask == 0) { in intel_get_shared_dpll()
4154 crtc->base.base.id, pll->name); in intel_get_shared_dpll()
4162 if (pll->new_config->crtc_mask == 0) in intel_get_shared_dpll()
4163 pll->new_config->hw_state = crtc_state->dpll_hw_state; in intel_get_shared_dpll()
4166 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, in intel_get_shared_dpll()
4169 pll->new_config->crtc_mask |= 1 << crtc->pipe; in intel_get_shared_dpll()
4171 return pll; in intel_get_shared_dpll()
4185 struct intel_shared_dpll *pll; in intel_shared_dpll_start_config() local
4189 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_start_config()
4191 pll->new_config = kmemdup(&pll->config, sizeof pll->config, in intel_shared_dpll_start_config()
4193 if (!pll->new_config) in intel_shared_dpll_start_config()
4196 pll->new_config->crtc_mask &= ~clear_pipes; in intel_shared_dpll_start_config()
4203 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_start_config()
4204 kfree(pll->new_config); in intel_shared_dpll_start_config()
4205 pll->new_config = NULL; in intel_shared_dpll_start_config()
4213 struct intel_shared_dpll *pll; in intel_shared_dpll_commit() local
4217 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_commit()
4219 WARN_ON(pll->new_config == &pll->config); in intel_shared_dpll_commit()
4221 pll->config = *pll->new_config; in intel_shared_dpll_commit()
4222 kfree(pll->new_config); in intel_shared_dpll_commit()
4223 pll->new_config = NULL; in intel_shared_dpll_commit()
4229 struct intel_shared_dpll *pll; in intel_shared_dpll_abort_config() local
4233 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_abort_config()
4235 WARN_ON(pll->new_config == &pll->config); in intel_shared_dpll_abort_config()
4237 kfree(pll->new_config); in intel_shared_dpll_abort_config()
4238 pll->new_config = NULL; in intel_shared_dpll_abort_config()
7845 struct intel_shared_dpll *pll; in ironlake_crtc_compute_clock() local
7884 pll = intel_get_shared_dpll(crtc, crtc_state); in ironlake_crtc_compute_clock()
7885 if (pll == NULL) { in ironlake_crtc_compute_clock()
8208 struct intel_shared_dpll *pll; in ironlake_get_pipe_config() local
8229 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in ironlake_get_pipe_config()
8231 WARN_ON(!pll->get_hw_state(dev_priv, pll, in ironlake_get_pipe_config()
8536 struct intel_shared_dpll *pll; in haswell_get_ddi_port_state() local
8550 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in haswell_get_ddi_port_state()
8552 WARN_ON(!pll->get_hw_state(dev_priv, pll, in haswell_get_ddi_port_state()
11330 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in check_shared_dpll_state() local
11336 DRM_DEBUG_KMS("%s\n", pll->name); in check_shared_dpll_state()
11338 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); in check_shared_dpll_state()
11340 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), in check_shared_dpll_state()
11342 pll->active, hweight32(pll->config.crtc_mask)); in check_shared_dpll_state()
11343 I915_STATE_WARN(pll->active && !pll->on, in check_shared_dpll_state()
11345 I915_STATE_WARN(pll->on && !pll->active, in check_shared_dpll_state()
11347 I915_STATE_WARN(pll->on != active, in check_shared_dpll_state()
11349 pll->on, active); in check_shared_dpll_state()
11352 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) in check_shared_dpll_state()
11354 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) in check_shared_dpll_state()
11357 I915_STATE_WARN(pll->active != active_crtcs, in check_shared_dpll_state()
11359 pll->active, active_crtcs); in check_shared_dpll_state()
11360 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, in check_shared_dpll_state()
11362 hweight32(pll->config.crtc_mask), enabled_crtcs); in check_shared_dpll_state()
11364 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, in check_shared_dpll_state()
12241 struct intel_shared_dpll *pll, in ibx_pch_dpll_get_hw_state() argument
12249 val = I915_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_get_hw_state()
12251 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); in ibx_pch_dpll_get_hw_state()
12252 hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); in ibx_pch_dpll_get_hw_state()
12258 struct intel_shared_dpll *pll) in ibx_pch_dpll_mode_set() argument
12260 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); in ibx_pch_dpll_mode_set()
12261 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); in ibx_pch_dpll_mode_set()
12265 struct intel_shared_dpll *pll) in ibx_pch_dpll_enable() argument
12270 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); in ibx_pch_dpll_enable()
12273 POSTING_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_enable()
12281 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); in ibx_pch_dpll_enable()
12282 POSTING_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_enable()
12287 struct intel_shared_dpll *pll) in ibx_pch_dpll_disable() argument
12294 if (intel_crtc_to_shared_dpll(crtc) == pll) in ibx_pch_dpll_disable()
12298 I915_WRITE(PCH_DPLL(pll->id), 0); in ibx_pch_dpll_disable()
12299 POSTING_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_disable()
14157 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_readout_hw_state() local
14159 pll->on = pll->get_hw_state(dev_priv, pll, in intel_modeset_readout_hw_state()
14160 &pll->config.hw_state); in intel_modeset_readout_hw_state()
14161 pll->active = 0; in intel_modeset_readout_hw_state()
14162 pll->config.crtc_mask = 0; in intel_modeset_readout_hw_state()
14164 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { in intel_modeset_readout_hw_state()
14165 pll->active++; in intel_modeset_readout_hw_state()
14166 pll->config.crtc_mask |= 1 << crtc->pipe; in intel_modeset_readout_hw_state()
14171 pll->name, pll->config.crtc_mask, pll->on); in intel_modeset_readout_hw_state()
14173 if (pll->config.crtc_mask) in intel_modeset_readout_hw_state()
14255 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_setup_hw_state() local
14257 if (!pll->on || pll->active) in intel_modeset_setup_hw_state()
14260 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); in intel_modeset_setup_hw_state()
14262 pll->disable(dev_priv, pll); in intel_modeset_setup_hw_state()
14263 pll->on = false; in intel_modeset_setup_hw_state()