262 	clkcfg = I915_READ(CLKCFG);  in intel_hrawclk()
334 	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,  in vlv_power_sequencer_kick()
345 	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;  in vlv_power_sequencer_kick()
355 	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;  in vlv_power_sequencer_kick()
454 	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;  in vlv_pipe_has_pp_on()
460 	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;  in vlv_pipe_has_vdd_on()
477 		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &  in vlv_initial_pps_pipe()
600 		pp_div = I915_READ(pp_div_reg);  in edp_notify_handler()
625 	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;  in edp_have_panel_power()
639 	return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;  in edp_have_panel_vdd()
654 			      I915_READ(_pp_stat_reg(intel_dp)),  in intel_dp_check_edp()
655 			      I915_READ(_pp_ctrl_reg(intel_dp)));  in intel_dp_check_edp()
842 		     I915_READ(ch_ctl));  in intel_dp_aux_ch()
918 		intel_dp_unpack_aux(I915_READ(ch_data + i),  in intel_dp_aux_ch()
1495 	dpa_ctl = I915_READ(DP_A);  in ironlake_set_pll_cpu_edp()
1545 	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;  in intel_dp_prepare()
1615 			I915_READ(pp_stat_reg),  in wait_panel_status()
1616 			I915_READ(pp_ctrl_reg));  in wait_panel_status()
1618 	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {  in wait_panel_status()
1620 				I915_READ(pp_stat_reg),  in wait_panel_status()
1621 				I915_READ(pp_ctrl_reg));  in wait_panel_status()
1675 	control = I915_READ(_pp_ctrl_reg(intel_dp));  in ironlake_get_pp_control()
1726 			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));  in edp_panel_vdd_on()
1793 	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));  in edp_panel_vdd_off_sync()
2082 	dpa_ctl = I915_READ(DP_A);  in ironlake_edp_pll_on()
2107 	dpa_ctl = I915_READ(DP_A);  in ironlake_edp_pll_off()
2166 	tmp = I915_READ(intel_dp->output_reg);  in intel_dp_get_hw_state()
2197 			trans_dp = I915_READ(TRANS_DP_CTL(i));  in intel_dp_get_hw_state()
2222 	tmp = I915_READ(intel_dp->output_reg);  in intel_dp_get_config()
2237 		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));  in intel_dp_get_config()
2260 		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)  in intel_dp_get_config()
2383 		uint32_t temp = I915_READ(DP_TP_CTL(port));  in _intel_dp_set_link_train()
2485 	uint32_t dp_reg = I915_READ(intel_dp->output_reg);  in intel_enable_dp()
3517 	val = I915_READ(DP_TP_CTL(port));  in intel_dp_set_idle_link_train()
3532 	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),  in intel_dp_set_idle_link_train()
3729 	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))  in intel_dp_link_down()
3747 	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {  in intel_dp_link_down()
4203 	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)  in g4x_digital_port_connected()
4838 	pp_on = I915_READ(pp_on_reg);  in intel_dp_init_panel_power_sequencer()
4839 	pp_off = I915_READ(pp_off_reg);  in intel_dp_init_panel_power_sequencer()
4840 	pp_div = I915_READ(pp_div_reg);  in intel_dp_init_panel_power_sequencer()
4967 		      I915_READ(pp_on_reg),  in intel_dp_init_panel_power_sequencer_registers()
4968 		      I915_READ(pp_off_reg),  in intel_dp_init_panel_power_sequencer_registers()
4969 		      I915_READ(pp_div_reg));  in intel_dp_init_panel_power_sequencer_registers()
5055 		val = I915_READ(reg);  in intel_dp_set_drrs_state()
5482 	intel_dp->DP = I915_READ(intel_dp->output_reg);  in intel_dp_init_connector()
5587 		u32 temp = I915_READ(PEG_BAND_GAP_DATA);  in intel_dp_init_connector()