34 					struct intel_crtc_state *pipe_config)  in intel_dp_mst_compute_config()  argument
42 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;  in intel_dp_mst_compute_config()
46 	pipe_config->dp_encoder_is_mst = true;  in intel_dp_mst_compute_config()
47 	pipe_config->has_pch_encoder = false;  in intel_dp_mst_compute_config()
48 	pipe_config->has_dp_encoder = true;  in intel_dp_mst_compute_config()
68 	pipe_config->pipe_bpp = 24;  in intel_dp_mst_compute_config()
69 	pipe_config->port_clock = rate;  in intel_dp_mst_compute_config()
71 	state = pipe_config->base.state;  in intel_dp_mst_compute_config()
90 	pipe_config->pbn = mst_pbn;  in intel_dp_mst_compute_config()
95 			       pipe_config->port_clock,  in intel_dp_mst_compute_config()
96 			       &pipe_config->dp_m_n);  in intel_dp_mst_compute_config()
98 	pipe_config->dp_m_n.tu = slots;  in intel_dp_mst_compute_config()
237 					struct intel_crtc_state *pipe_config)  in intel_dp_mst_enc_get_config()  argument
244 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_dp_mst_enc_get_config()
247 	pipe_config->has_dp_encoder = true;  in intel_dp_mst_enc_get_config()
261 		pipe_config->pipe_bpp = 18;  in intel_dp_mst_enc_get_config()
264 		pipe_config->pipe_bpp = 24;  in intel_dp_mst_enc_get_config()
267 		pipe_config->pipe_bpp = 30;  in intel_dp_mst_enc_get_config()
270 		pipe_config->pipe_bpp = 36;  in intel_dp_mst_enc_get_config()
275 	pipe_config->base.adjusted_mode.flags |= flags;  in intel_dp_mst_enc_get_config()
276 	intel_dp_get_m_n(crtc, pipe_config);  in intel_dp_mst_enc_get_config()
278 	intel_ddi_clock_get(&intel_dig_port->base, pipe_config);  in intel_dp_mst_enc_get_config()