140 	u32 val = I915_READ(VIDEO_DIP_CTL);  in g4x_write_infoframe()  local
143 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");  in g4x_write_infoframe()
145 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */  in g4x_write_infoframe()
146 	val |= g4x_infoframe_index(type);  in g4x_write_infoframe()
148 	val &= ~g4x_infoframe_enable(type);  in g4x_write_infoframe()
150 	I915_WRITE(VIDEO_DIP_CTL, val);  in g4x_write_infoframe()
162 	val |= g4x_infoframe_enable(type);  in g4x_write_infoframe()
163 	val &= ~VIDEO_DIP_FREQ_MASK;  in g4x_write_infoframe()
164 	val |= VIDEO_DIP_FREQ_VSYNC;  in g4x_write_infoframe()
166 	I915_WRITE(VIDEO_DIP_CTL, val);  in g4x_write_infoframe()
175 	u32 val = I915_READ(VIDEO_DIP_CTL);  in g4x_infoframe_enabled()  local
177 	if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))  in g4x_infoframe_enabled()
178 		return val & VIDEO_DIP_ENABLE;  in g4x_infoframe_enabled()
192 	u32 val = I915_READ(reg);  in ibx_write_infoframe()  local
194 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");  in ibx_write_infoframe()
196 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */  in ibx_write_infoframe()
197 	val |= g4x_infoframe_index(type);  in ibx_write_infoframe()
199 	val &= ~g4x_infoframe_enable(type);  in ibx_write_infoframe()
201 	I915_WRITE(reg, val);  in ibx_write_infoframe()
213 	val |= g4x_infoframe_enable(type);  in ibx_write_infoframe()
214 	val &= ~VIDEO_DIP_FREQ_MASK;  in ibx_write_infoframe()
215 	val |= VIDEO_DIP_FREQ_VSYNC;  in ibx_write_infoframe()
217 	I915_WRITE(reg, val);  in ibx_write_infoframe()
227 	u32 val = I915_READ(reg);  in ibx_infoframe_enabled()  local
229 	return val & VIDEO_DIP_ENABLE;  in ibx_infoframe_enabled()
241 	u32 val = I915_READ(reg);  in cpt_write_infoframe()  local
243 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");  in cpt_write_infoframe()
245 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */  in cpt_write_infoframe()
246 	val |= g4x_infoframe_index(type);  in cpt_write_infoframe()
251 		val &= ~g4x_infoframe_enable(type);  in cpt_write_infoframe()
253 	I915_WRITE(reg, val);  in cpt_write_infoframe()
265 	val |= g4x_infoframe_enable(type);  in cpt_write_infoframe()
266 	val &= ~VIDEO_DIP_FREQ_MASK;  in cpt_write_infoframe()
267 	val |= VIDEO_DIP_FREQ_VSYNC;  in cpt_write_infoframe()
269 	I915_WRITE(reg, val);  in cpt_write_infoframe()
279 	u32 val = I915_READ(reg);  in cpt_infoframe_enabled()  local
281 	return val & VIDEO_DIP_ENABLE;  in cpt_infoframe_enabled()
293 	u32 val = I915_READ(reg);  in vlv_write_infoframe()  local
295 	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");  in vlv_write_infoframe()
297 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */  in vlv_write_infoframe()
298 	val |= g4x_infoframe_index(type);  in vlv_write_infoframe()
300 	val &= ~g4x_infoframe_enable(type);  in vlv_write_infoframe()
302 	I915_WRITE(reg, val);  in vlv_write_infoframe()
314 	val |= g4x_infoframe_enable(type);  in vlv_write_infoframe()
315 	val &= ~VIDEO_DIP_FREQ_MASK;  in vlv_write_infoframe()
316 	val |= VIDEO_DIP_FREQ_VSYNC;  in vlv_write_infoframe()
318 	I915_WRITE(reg, val);  in vlv_write_infoframe()
328 	u32 val = I915_READ(reg);  in vlv_infoframe_enabled()  local
330 	return val & VIDEO_DIP_ENABLE;  in vlv_infoframe_enabled()
344 	u32 val = I915_READ(ctl_reg);  in hsw_write_infoframe()  local
352 	val &= ~hsw_infoframe_enable(type);  in hsw_write_infoframe()
353 	I915_WRITE(ctl_reg, val);  in hsw_write_infoframe()
365 	val |= hsw_infoframe_enable(type);  in hsw_write_infoframe()
366 	I915_WRITE(ctl_reg, val);  in hsw_write_infoframe()
376 	u32 val = I915_READ(ctl_reg);  in hsw_infoframe_enabled()  local
378 	return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |  in hsw_infoframe_enabled()
490 	u32 val = I915_READ(reg);  in g4x_set_infoframes()  local
504 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;  in g4x_set_infoframes()
507 		if (!(val & VIDEO_DIP_ENABLE))  in g4x_set_infoframes()
509 		val &= ~VIDEO_DIP_ENABLE;  in g4x_set_infoframes()
510 		I915_WRITE(reg, val);  in g4x_set_infoframes()
515 	if (port != (val & VIDEO_DIP_PORT_MASK)) {  in g4x_set_infoframes()
516 		if (val & VIDEO_DIP_ENABLE) {  in g4x_set_infoframes()
517 			val &= ~VIDEO_DIP_ENABLE;  in g4x_set_infoframes()
518 			I915_WRITE(reg, val);  in g4x_set_infoframes()
521 		val &= ~VIDEO_DIP_PORT_MASK;  in g4x_set_infoframes()
522 		val |= port;  in g4x_set_infoframes()
525 	val |= VIDEO_DIP_ENABLE;  in g4x_set_infoframes()
526 	val &= ~VIDEO_DIP_ENABLE_VENDOR;  in g4x_set_infoframes()
528 	I915_WRITE(reg, val);  in g4x_set_infoframes()
545 	u32 val = I915_READ(reg);  in ibx_set_infoframes()  local
551 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;  in ibx_set_infoframes()
554 		if (!(val & VIDEO_DIP_ENABLE))  in ibx_set_infoframes()
556 		val &= ~VIDEO_DIP_ENABLE;  in ibx_set_infoframes()
557 		I915_WRITE(reg, val);  in ibx_set_infoframes()
562 	if (port != (val & VIDEO_DIP_PORT_MASK)) {  in ibx_set_infoframes()
563 		if (val & VIDEO_DIP_ENABLE) {  in ibx_set_infoframes()
564 			val &= ~VIDEO_DIP_ENABLE;  in ibx_set_infoframes()
565 			I915_WRITE(reg, val);  in ibx_set_infoframes()
568 		val &= ~VIDEO_DIP_PORT_MASK;  in ibx_set_infoframes()
569 		val |= port;  in ibx_set_infoframes()
572 	val |= VIDEO_DIP_ENABLE;  in ibx_set_infoframes()
573 	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |  in ibx_set_infoframes()
576 	I915_WRITE(reg, val);  in ibx_set_infoframes()
592 	u32 val = I915_READ(reg);  in cpt_set_infoframes()  local
597 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;  in cpt_set_infoframes()
600 		if (!(val & VIDEO_DIP_ENABLE))  in cpt_set_infoframes()
602 		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);  in cpt_set_infoframes()
603 		I915_WRITE(reg, val);  in cpt_set_infoframes()
609 	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;  in cpt_set_infoframes()
610 	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |  in cpt_set_infoframes()
613 	I915_WRITE(reg, val);  in cpt_set_infoframes()
630 	u32 val = I915_READ(reg);  in vlv_set_infoframes()  local
636 	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;  in vlv_set_infoframes()
639 		if (!(val & VIDEO_DIP_ENABLE))  in vlv_set_infoframes()
641 		val &= ~VIDEO_DIP_ENABLE;  in vlv_set_infoframes()
642 		I915_WRITE(reg, val);  in vlv_set_infoframes()
647 	if (port != (val & VIDEO_DIP_PORT_MASK)) {  in vlv_set_infoframes()
648 		if (val & VIDEO_DIP_ENABLE) {  in vlv_set_infoframes()
649 			val &= ~VIDEO_DIP_ENABLE;  in vlv_set_infoframes()
650 			I915_WRITE(reg, val);  in vlv_set_infoframes()
653 		val &= ~VIDEO_DIP_PORT_MASK;  in vlv_set_infoframes()
654 		val |= port;  in vlv_set_infoframes()
657 	val |= VIDEO_DIP_ENABLE;  in vlv_set_infoframes()
658 	val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |  in vlv_set_infoframes()
661 	I915_WRITE(reg, val);  in vlv_set_infoframes()
677 	u32 val = I915_READ(reg);  in hsw_set_infoframes()  local
687 	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |  in hsw_set_infoframes()
690 	I915_WRITE(reg, val);  in hsw_set_infoframes()
1176 			uint64_t val)  in intel_hdmi_set_property()  argument
1184 	ret = drm_object_property_set_value(&connector->base, property, val);  in intel_hdmi_set_property()
1189 		enum hdmi_force_audio i = val;  in intel_hdmi_set_property()
1213 		switch (val) {  in intel_hdmi_set_property()
1237 		switch (val) {  in intel_hdmi_set_property()
1288 	u32 val;  in vlv_hdmi_pre_enable()  local
1292 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));  in vlv_hdmi_pre_enable()
1293 	val = 0;  in vlv_hdmi_pre_enable()
1295 		val |= (1<<21);  in vlv_hdmi_pre_enable()
1297 		val &= ~(1<<21);  in vlv_hdmi_pre_enable()
1298 	val |= 0x001000c4;  in vlv_hdmi_pre_enable()
1299 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);  in vlv_hdmi_pre_enable()
1367 	u32 val;  in chv_hdmi_pre_pll_enable()  local
1375 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);  in chv_hdmi_pre_pll_enable()
1376 		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);  in chv_hdmi_pre_pll_enable()
1378 			val |= CHV_BUFLEFTENA1_FORCE;  in chv_hdmi_pre_pll_enable()
1380 			val |= CHV_BUFRIGHTENA1_FORCE;  in chv_hdmi_pre_pll_enable()
1381 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);  in chv_hdmi_pre_pll_enable()
1383 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);  in chv_hdmi_pre_pll_enable()
1384 		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);  in chv_hdmi_pre_pll_enable()
1386 			val |= CHV_BUFLEFTENA2_FORCE;  in chv_hdmi_pre_pll_enable()
1388 			val |= CHV_BUFRIGHTENA2_FORCE;  in chv_hdmi_pre_pll_enable()
1389 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);  in chv_hdmi_pre_pll_enable()
1393 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));  in chv_hdmi_pre_pll_enable()
1394 	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;  in chv_hdmi_pre_pll_enable()
1396 		val &= ~CHV_PCS_USEDCLKCHANNEL;  in chv_hdmi_pre_pll_enable()
1398 		val |= CHV_PCS_USEDCLKCHANNEL;  in chv_hdmi_pre_pll_enable()
1399 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);  in chv_hdmi_pre_pll_enable()
1401 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));  in chv_hdmi_pre_pll_enable()
1402 	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;  in chv_hdmi_pre_pll_enable()
1404 		val &= ~CHV_PCS_USEDCLKCHANNEL;  in chv_hdmi_pre_pll_enable()
1406 		val |= CHV_PCS_USEDCLKCHANNEL;  in chv_hdmi_pre_pll_enable()
1407 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);  in chv_hdmi_pre_pll_enable()
1414 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));  in chv_hdmi_pre_pll_enable()
1416 		val &= ~CHV_CMN_USEDCLKCHANNEL;  in chv_hdmi_pre_pll_enable()
1418 		val |= CHV_CMN_USEDCLKCHANNEL;  in chv_hdmi_pre_pll_enable()
1419 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);  in chv_hdmi_pre_pll_enable()
1449 	u32 val;  in chv_hdmi_post_disable()  local
1454 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_hdmi_post_disable()
1455 	val |= CHV_PCS_REQ_SOFTRESET_EN;  in chv_hdmi_post_disable()
1456 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_hdmi_post_disable()
1458 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_hdmi_post_disable()
1459 	val |= CHV_PCS_REQ_SOFTRESET_EN;  in chv_hdmi_post_disable()
1460 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_hdmi_post_disable()
1462 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_hdmi_post_disable()
1463 	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);  in chv_hdmi_post_disable()
1464 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_hdmi_post_disable()
1466 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_hdmi_post_disable()
1467 	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);  in chv_hdmi_post_disable()
1468 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_hdmi_post_disable()
1486 	u32 val;  in chv_hdmi_pre_enable()  local
1491 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));  in chv_hdmi_pre_enable()
1492 	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;  in chv_hdmi_pre_enable()
1493 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);  in chv_hdmi_pre_enable()
1495 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));  in chv_hdmi_pre_enable()
1496 	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;  in chv_hdmi_pre_enable()
1497 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);  in chv_hdmi_pre_enable()
1500 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_hdmi_pre_enable()
1501 	val |= CHV_PCS_REQ_SOFTRESET_EN;  in chv_hdmi_pre_enable()
1502 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_hdmi_pre_enable()
1504 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_hdmi_pre_enable()
1505 	val |= CHV_PCS_REQ_SOFTRESET_EN;  in chv_hdmi_pre_enable()
1506 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_hdmi_pre_enable()
1508 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_hdmi_pre_enable()
1509 	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);  in chv_hdmi_pre_enable()
1510 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_hdmi_pre_enable()
1512 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_hdmi_pre_enable()
1513 	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);  in chv_hdmi_pre_enable()
1514 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_hdmi_pre_enable()
1528 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in chv_hdmi_pre_enable()
1529 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);  in chv_hdmi_pre_enable()
1530 	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);  in chv_hdmi_pre_enable()
1531 	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;  in chv_hdmi_pre_enable()
1532 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in chv_hdmi_pre_enable()
1534 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in chv_hdmi_pre_enable()
1535 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);  in chv_hdmi_pre_enable()
1536 	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);  in chv_hdmi_pre_enable()
1537 	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;  in chv_hdmi_pre_enable()
1538 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in chv_hdmi_pre_enable()
1540 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));  in chv_hdmi_pre_enable()
1541 	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);  in chv_hdmi_pre_enable()
1542 	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;  in chv_hdmi_pre_enable()
1543 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);  in chv_hdmi_pre_enable()
1545 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));  in chv_hdmi_pre_enable()
1546 	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);  in chv_hdmi_pre_enable()
1547 	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;  in chv_hdmi_pre_enable()
1548 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);  in chv_hdmi_pre_enable()
1553 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));  in chv_hdmi_pre_enable()
1554 		val &= ~DPIO_SWING_DEEMPH9P5_MASK;  in chv_hdmi_pre_enable()
1555 		val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;  in chv_hdmi_pre_enable()
1556 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);  in chv_hdmi_pre_enable()
1560 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));  in chv_hdmi_pre_enable()
1561 		val &= ~DPIO_SWING_MARGIN000_MASK;  in chv_hdmi_pre_enable()
1562 		val |= 102 << DPIO_SWING_MARGIN000_SHIFT;  in chv_hdmi_pre_enable()
1563 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);  in chv_hdmi_pre_enable()
1568 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));  in chv_hdmi_pre_enable()
1569 		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;  in chv_hdmi_pre_enable()
1570 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);  in chv_hdmi_pre_enable()
1575 	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));  in chv_hdmi_pre_enable()
1577 		val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;  in chv_hdmi_pre_enable()
1579 		val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;  in chv_hdmi_pre_enable()
1580 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);  in chv_hdmi_pre_enable()
1587 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in chv_hdmi_pre_enable()
1588 	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;  in chv_hdmi_pre_enable()
1589 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in chv_hdmi_pre_enable()
1591 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in chv_hdmi_pre_enable()
1592 	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;  in chv_hdmi_pre_enable()
1593 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in chv_hdmi_pre_enable()
1596 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);  in chv_hdmi_pre_enable()
1597 	val |= DPIO_LRC_BYPASS;  in chv_hdmi_pre_enable()
1598 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);  in chv_hdmi_pre_enable()