326 	uint32_t *reg_state;  in execlists_update_context()  local
329 	reg_state = kmap_atomic(page);  in execlists_update_context()
331 	reg_state[CTX_RING_TAIL+1] = tail;  in execlists_update_context()
332 	reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);  in execlists_update_context()
334 	kunmap_atomic(reg_state);  in execlists_update_context()
1733 	uint32_t *reg_state;  in populate_lr_context()  local
1756 	reg_state = kmap_atomic(page);  in populate_lr_context()
1764 		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);  in populate_lr_context()
1766 		reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);  in populate_lr_context()
1767 	reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;  in populate_lr_context()
1768 	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);  in populate_lr_context()
1769 	reg_state[CTX_CONTEXT_CONTROL+1] =  in populate_lr_context()
1772 	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);  in populate_lr_context()
1773 	reg_state[CTX_RING_HEAD+1] = 0;  in populate_lr_context()
1774 	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);  in populate_lr_context()
1775 	reg_state[CTX_RING_TAIL+1] = 0;  in populate_lr_context()
1776 	reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);  in populate_lr_context()
1780 	reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);  in populate_lr_context()
1781 	reg_state[CTX_RING_BUFFER_CONTROL+1] =  in populate_lr_context()
1783 	reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;  in populate_lr_context()
1784 	reg_state[CTX_BB_HEAD_U+1] = 0;  in populate_lr_context()
1785 	reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;  in populate_lr_context()
1786 	reg_state[CTX_BB_HEAD_L+1] = 0;  in populate_lr_context()
1787 	reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;  in populate_lr_context()
1788 	reg_state[CTX_BB_STATE+1] = (1<<5);  in populate_lr_context()
1789 	reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;  in populate_lr_context()
1790 	reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;  in populate_lr_context()
1791 	reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;  in populate_lr_context()
1792 	reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;  in populate_lr_context()
1793 	reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;  in populate_lr_context()
1794 	reg_state[CTX_SECOND_BB_STATE+1] = 0;  in populate_lr_context()
1799 		reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;  in populate_lr_context()
1800 		reg_state[CTX_BB_PER_CTX_PTR+1] = 0;  in populate_lr_context()
1801 		reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;  in populate_lr_context()
1802 		reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;  in populate_lr_context()
1803 		reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;  in populate_lr_context()
1804 		reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;  in populate_lr_context()
1806 	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);  in populate_lr_context()
1807 	reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;  in populate_lr_context()
1808 	reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;  in populate_lr_context()
1809 	reg_state[CTX_CTX_TIMESTAMP+1] = 0;  in populate_lr_context()
1810 	reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);  in populate_lr_context()
1811 	reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);  in populate_lr_context()
1812 	reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);  in populate_lr_context()
1813 	reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);  in populate_lr_context()
1814 	reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);  in populate_lr_context()
1815 	reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);  in populate_lr_context()
1816 	reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);  in populate_lr_context()
1817 	reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);  in populate_lr_context()
1818 	reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[3]->daddr);  in populate_lr_context()
1819 	reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[3]->daddr);  in populate_lr_context()
1820 	reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[2]->daddr);  in populate_lr_context()
1821 	reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[2]->daddr);  in populate_lr_context()
1822 	reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[1]->daddr);  in populate_lr_context()
1823 	reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[1]->daddr);  in populate_lr_context()
1824 	reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[0]->daddr);  in populate_lr_context()
1825 	reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[0]->daddr);  in populate_lr_context()
1827 		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);  in populate_lr_context()
1828 		reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;  in populate_lr_context()
1829 		reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);  in populate_lr_context()
1832 	kunmap_atomic(reg_state);  in populate_lr_context()
2050 		uint32_t *reg_state;  in intel_lr_context_reset()  local
2061 		reg_state = kmap_atomic(page);  in intel_lr_context_reset()
2063 		reg_state[CTX_RING_HEAD+1] = 0;  in intel_lr_context_reset()
2064 		reg_state[CTX_RING_TAIL+1] = 0;  in intel_lr_context_reset()
2066 		kunmap_atomic(reg_state);  in intel_lr_context_reset()