622 	struct drm_crtc *crtc, *enabled = NULL;  in single_enabled_crtc()  local
624 	for_each_crtc(dev, crtc) {  in single_enabled_crtc()
625 		if (intel_crtc_active(crtc)) {  in single_enabled_crtc()
628 			enabled = crtc;  in single_enabled_crtc()
639 	struct drm_crtc *crtc;  in pineview_update_wm()  local
652 	crtc = single_enabled_crtc(dev);  in pineview_update_wm()
653 	if (crtc) {  in pineview_update_wm()
655 		int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;  in pineview_update_wm()
658 		adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in pineview_update_wm()
714 	struct drm_crtc *crtc;  in g4x_compute_wm0()  local
720 	crtc = intel_get_crtc_for_plane(dev, plane);  in g4x_compute_wm0()
721 	if (!intel_crtc_active(crtc)) {  in g4x_compute_wm0()
727 	adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in g4x_compute_wm0()
730 	hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;  in g4x_compute_wm0()
731 	pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;  in g4x_compute_wm0()
746 	entries = line_count * crtc->cursor->state->crtc_w * pixel_size;  in g4x_compute_wm0()
800 	struct drm_crtc *crtc;  in g4x_compute_srwm()  local
813 	crtc = intel_get_crtc_for_plane(dev, plane);  in g4x_compute_srwm()
814 	adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in g4x_compute_srwm()
817 	hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;  in g4x_compute_srwm()
818 	pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;  in g4x_compute_srwm()
832 	entries = line_count * pixel_size * crtc->cursor->state->crtc_w;  in g4x_compute_srwm()
844 static void vlv_write_wm_values(struct intel_crtc *crtc,  in vlv_write_wm_values()  argument
847 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in vlv_write_wm_values()
848 	enum pipe pipe = crtc->pipe;  in vlv_write_wm_values()
910 static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,  in vlv_compute_drain_latency()  argument
913 	struct drm_device *dev = crtc->dev;  in vlv_compute_drain_latency()
914 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in vlv_compute_drain_latency()
951 static int vlv_compute_wm(struct intel_crtc *crtc,  in vlv_compute_wm()  argument
961 	if (!crtc->active || !plane->base.state->fb)  in vlv_compute_wm()
965 	clock = crtc->config->base.adjusted_mode.crtc_clock;  in vlv_compute_wm()
985 	struct drm_crtc *crtc;  in vlv_compute_sr_wm()  local
993 	crtc = single_enabled_crtc(dev);  in vlv_compute_sr_wm()
995 	if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {  in vlv_compute_sr_wm()
996 		pipe = to_intel_crtc(crtc)->pipe;  in vlv_compute_sr_wm()
1006 	wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),  in vlv_compute_sr_wm()
1007 				       to_intel_plane(crtc->cursor), 0x3f);  in vlv_compute_sr_wm()
1016 		wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),  in vlv_compute_sr_wm()
1025 static void valleyview_update_wm(struct drm_crtc *crtc)  in valleyview_update_wm()  argument
1027 	struct drm_device *dev = crtc->dev;  in valleyview_update_wm()
1029 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in valleyview_update_wm()
1034 	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);  in valleyview_update_wm()
1036 					       to_intel_plane(crtc->primary),  in valleyview_update_wm()
1039 	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);  in valleyview_update_wm()
1041 					      to_intel_plane(crtc->cursor),  in valleyview_update_wm()
1075 					struct drm_crtc *crtc,  in valleyview_update_sprite_wm()  argument
1081 	struct drm_device *dev = crtc->dev;  in valleyview_update_sprite_wm()
1083 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in valleyview_update_sprite_wm()
1091 			vlv_compute_drain_latency(crtc, plane);  in valleyview_update_sprite_wm()
1124 static void g4x_update_wm(struct drm_crtc *crtc)  in g4x_update_wm()  argument
1126 	struct drm_device *dev = crtc->dev;  in g4x_update_wm()
1186 	struct drm_crtc *crtc;  in i965_update_wm()  local
1192 	crtc = single_enabled_crtc(dev);  in i965_update_wm()
1193 	if (crtc) {  in i965_update_wm()
1197 			&to_intel_crtc(crtc)->config->base.adjusted_mode;  in i965_update_wm()
1200 		int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;  in i965_update_wm()
1201 		int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;  in i965_update_wm()
1219 			pixel_size * crtc->cursor->state->crtc_w;  in i965_update_wm()
1267 	struct drm_crtc *crtc, *enabled = NULL;  in i9xx_update_wm()  local
1277 	crtc = intel_get_crtc_for_plane(dev, 0);  in i9xx_update_wm()
1278 	if (intel_crtc_active(crtc)) {  in i9xx_update_wm()
1280 		int cpp = crtc->primary->state->fb->bits_per_pixel / 8;  in i9xx_update_wm()
1284 		adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in i9xx_update_wm()
1288 		enabled = crtc;  in i9xx_update_wm()
1299 	crtc = intel_get_crtc_for_plane(dev, 1);  in i9xx_update_wm()
1300 	if (intel_crtc_active(crtc)) {  in i9xx_update_wm()
1302 		int cpp = crtc->primary->state->fb->bits_per_pixel / 8;  in i9xx_update_wm()
1306 		adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in i9xx_update_wm()
1311 			enabled = crtc;  in i9xx_update_wm()
1392 	struct drm_crtc *crtc;  in i845_update_wm()  local
1397 	crtc = single_enabled_crtc(dev);  in i845_update_wm()
1398 	if (crtc == NULL)  in i845_update_wm()
1401 	adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;  in i845_update_wm()
1415 				    struct drm_crtc *crtc)  in ilk_pipe_pixel_rate()  argument
1417 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_pipe_pixel_rate()
1779 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)  in hsw_compute_linetime_wm()  argument
1782 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in hsw_compute_linetime_wm()
2033 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,  in ilk_compute_wm_parameters()  argument
2036 	struct drm_device *dev = crtc->dev;  in ilk_compute_wm_parameters()
2037 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_compute_wm_parameters()
2046 	p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);  in ilk_compute_wm_parameters()
2048 	if (crtc->primary->state->fb)  in ilk_compute_wm_parameters()
2050 			crtc->primary->state->fb->bits_per_pixel / 8;  in ilk_compute_wm_parameters()
2094 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,  in intel_compute_pipe_wm()  argument
2098 	struct drm_device *dev = crtc->dev;  in intel_compute_pipe_wm()
2124 		pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);  in intel_compute_pipe_wm()
2547 	struct drm_crtc *crtc;  in skl_ddb_get_pipe_allocation_limits()  local
2562 	for_each_crtc(dev, crtc) {  in skl_ddb_get_pipe_allocation_limits()
2563 		if (!to_intel_crtc(crtc)->active)  in skl_ddb_get_pipe_allocation_limits()
2566 		if (crtc == for_crtc)  in skl_ddb_get_pipe_allocation_limits()
2644 skl_allocate_pipe_ddb(struct drm_crtc *crtc,  in skl_allocate_pipe_ddb()  argument
2649 	struct drm_device *dev = crtc->dev;  in skl_allocate_pipe_ddb()
2651 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_allocate_pipe_ddb()
2659 	skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);  in skl_allocate_pipe_ddb()
2799 	struct drm_crtc *crtc;  in skl_compute_wm_global_parameters()  local
2802 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)  in skl_compute_wm_global_parameters()
2803 		config->num_pipes_active += to_intel_crtc(crtc)->active;  in skl_compute_wm_global_parameters()
2814 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,  in skl_compute_wm_pipe_parameters()  argument
2817 	struct drm_device *dev = crtc->dev;  in skl_compute_wm_pipe_parameters()
2818 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_compute_wm_pipe_parameters()
2829 		fb = crtc->primary->state->fb;  in skl_compute_wm_pipe_parameters()
2841 		p->plane[0].rotation = crtc->primary->state->rotation;  in skl_compute_wm_pipe_parameters()
2843 		fb = crtc->cursor->state->fb;  in skl_compute_wm_pipe_parameters()
2847 			p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;  in skl_compute_wm_pipe_parameters()
2848 			p->cursor.vert_pixels = crtc->cursor->state->crtc_h;  in skl_compute_wm_pipe_parameters()
2972 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)  in skl_compute_linetime_wm()  argument
2974 	if (!to_intel_crtc(crtc)->active)  in skl_compute_linetime_wm()
2981 static void skl_compute_transition_wm(struct drm_crtc *crtc,  in skl_compute_transition_wm()  argument
2985 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_compute_transition_wm()
2997 static void skl_compute_pipe_wm(struct drm_crtc *crtc,  in skl_compute_pipe_wm()  argument
3002 	struct drm_device *dev = crtc->dev;  in skl_compute_pipe_wm()
3004 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_compute_pipe_wm()
3012 	pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);  in skl_compute_pipe_wm()
3014 	skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);  in skl_compute_pipe_wm()
3088 	struct intel_crtc *crtc;  in skl_write_wm_values()  local
3090 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {  in skl_write_wm_values()
3092 		enum pipe pipe = crtc->pipe;  in skl_write_wm_values()
3100 			for (i = 0; i < intel_num_planes(crtc); i++)  in skl_write_wm_values()
3106 		for (i = 0; i < intel_num_planes(crtc); i++)  in skl_write_wm_values()
3111 		for (i = 0; i < intel_num_planes(crtc); i++)  in skl_write_wm_values()
3180 	struct intel_crtc *crtc;  in skl_flush_wm_values()  local
3193 	for_each_intel_crtc(dev, crtc) {  in skl_flush_wm_values()
3194 		if (!crtc->active)  in skl_flush_wm_values()
3197 		pipe = crtc->pipe;  in skl_flush_wm_values()
3216 	for_each_intel_crtc(dev, crtc) {  in skl_flush_wm_values()
3217 		if (!crtc->active)  in skl_flush_wm_values()
3220 		pipe = crtc->pipe;  in skl_flush_wm_values()
3239 	for_each_intel_crtc(dev, crtc) {  in skl_flush_wm_values()
3240 		if (!crtc->active)  in skl_flush_wm_values()
3243 		pipe = crtc->pipe;  in skl_flush_wm_values()
3256 static bool skl_update_pipe_wm(struct drm_crtc *crtc,  in skl_update_pipe_wm()  argument
3262 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_update_pipe_wm()
3264 	skl_compute_wm_pipe_parameters(crtc, params);  in skl_update_pipe_wm()
3265 	skl_allocate_pipe_ddb(crtc, config, params, ddb);  in skl_update_pipe_wm()
3266 	skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);  in skl_update_pipe_wm()
3276 				     struct drm_crtc *crtc,  in skl_update_other_pipe_wm()  argument
3281 	struct intel_crtc *this_crtc = to_intel_crtc(crtc);  in skl_update_other_pipe_wm()
3324 static void skl_update_wm(struct drm_crtc *crtc)  in skl_update_wm()  argument
3326 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_update_wm()
3327 	struct drm_device *dev = crtc->dev;  in skl_update_wm()
3338 	if (!skl_update_pipe_wm(crtc, &params, &config,  in skl_update_wm()
3345 	skl_update_other_pipe_wm(dev, crtc, &config, results);  in skl_update_wm()
3354 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,  in skl_update_sprite_wm()  argument
3375 	skl_update_wm(crtc);  in skl_update_sprite_wm()
3378 static void ilk_update_wm(struct drm_crtc *crtc)  in ilk_update_wm()  argument
3380 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_update_wm()
3381 	struct drm_device *dev = crtc->dev;  in ilk_update_wm()
3391 	ilk_compute_wm_parameters(crtc, &params);  in ilk_update_wm()
3393 	intel_compute_pipe_wm(crtc, &params, &pipe_wm);  in ilk_update_wm()
3426 		     struct drm_crtc *crtc,  in ilk_update_sprite_wm()  argument
3449 	ilk_update_wm(crtc);  in ilk_update_sprite_wm()
3496 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)  in skl_pipe_wm_get_hw_state()  argument
3498 	struct drm_device *dev = crtc->dev;  in skl_pipe_wm_get_hw_state()
3501 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_pipe_wm_get_hw_state()
3552 	struct drm_crtc *crtc;  in skl_wm_get_hw_state()  local
3555 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)  in skl_wm_get_hw_state()
3556 		skl_pipe_wm_get_hw_state(crtc);  in skl_wm_get_hw_state()
3559 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)  in ilk_pipe_wm_get_hw_state()  argument
3561 	struct drm_device *dev = crtc->dev;  in ilk_pipe_wm_get_hw_state()
3564 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_pipe_wm_get_hw_state()
3612 	struct drm_crtc *crtc;  in ilk_wm_get_hw_state()  local
3614 	for_each_crtc(dev, crtc)  in ilk_wm_get_hw_state()
3615 		ilk_pipe_wm_get_hw_state(crtc);  in ilk_wm_get_hw_state()
3670 void intel_update_watermarks(struct drm_crtc *crtc)  in intel_update_watermarks()  argument
3672 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;  in intel_update_watermarks()
3675 		dev_priv->display.update_wm(crtc);  in intel_update_watermarks()
3679 				    struct drm_crtc *crtc,  in intel_update_sprite_watermarks()  argument
3688 		dev_priv->display.update_sprite_wm(plane, crtc,  in intel_update_sprite_watermarks()