3857 		if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)  in gen6_set_rps_thresholds()
3862 		if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)  in gen6_set_rps_thresholds()
3864 		else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)  in gen6_set_rps_thresholds()
3869 		if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)  in gen6_set_rps_thresholds()
3964 	if (val != dev_priv->rps.cur_freq) {  in gen6_set_rps()
3988 	dev_priv->rps.cur_freq = val;  in gen6_set_rps()
4004 	if (val != dev_priv->rps.cur_freq)  in valleyview_set_rps()
4009 	dev_priv->rps.cur_freq = val;  in valleyview_set_rps()
4037 	if (dev_priv->rps.cur_freq <= val)  in vlv_set_rps_idle()
4046 	dev_priv->rps.cur_freq = val;  in vlv_set_rps_idle()
4066 			   gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));  in gen6_rps_busy()
4095 	    dev_priv->rps.cur_freq < val) {  in gen6_rps_boost()
4216 	dev_priv->rps.cur_freq		= 0;  in gen6_init_rps_frequencies()
5043 	dev_priv->rps.cur_freq = (val >> 8) & 0xff;  in cherryview_enable_rps()
5045 			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),  in cherryview_enable_rps()
5046 			 dev_priv->rps.cur_freq);  in cherryview_enable_rps()
5127 	dev_priv->rps.cur_freq = (val >> 8) & 0xff;  in valleyview_enable_rps()
5129 			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),  in valleyview_enable_rps()
5130 			 dev_priv->rps.cur_freq);  in valleyview_enable_rps()
5333 	pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));  in __i915_gfx_val()