716 	int htotal, hdisplay, clock, pixel_size;  in g4x_compute_wm0()  local
730 	hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;  in g4x_compute_wm0()
735 	tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;  in g4x_compute_wm0()
747 	tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;  in g4x_compute_wm0()
802 	int hdisplay, htotal, pixel_size, clock;  in g4x_compute_srwm()  local
817 	hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;  in g4x_compute_srwm()
822 	line_size = hdisplay * pixel_size;  in g4x_compute_srwm()
1200 		int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;  in i965_update_wm()  local
1209 			pixel_size * hdisplay;  in i965_update_wm()
1348 		int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;  in i9xx_update_wm()  local
1357 			pixel_size * hdisplay;  in i9xx_update_wm()