304 #define FW_WM(value, plane) \  argument
305 	(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
359 			      enum pipe pipe, int plane)  in vlv_get_fifo_size()  argument
388 	switch (plane) {  in vlv_get_fifo_size()
403 		      pipe_name(pipe), plane == 0 ? "primary" : "sprite",  in vlv_get_fifo_size()
404 		      plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),  in vlv_get_fifo_size()
410 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)  in i9xx_get_fifo_size()  argument
417 	if (plane)  in i9xx_get_fifo_size()
421 		      plane ? "B" : "A", size);  in i9xx_get_fifo_size()
426 static int i830_get_fifo_size(struct drm_device *dev, int plane)  in i830_get_fifo_size()  argument
433 	if (plane)  in i830_get_fifo_size()
438 		      plane ? "B" : "A", size);  in i830_get_fifo_size()
443 static int i845_get_fifo_size(struct drm_device *dev, int plane)  in i845_get_fifo_size()  argument
453 		      plane ? "B" : "A",  in i845_get_fifo_size()
706 			    int plane,  in g4x_compute_wm0()  argument
720 	crtc = intel_get_crtc_for_plane(dev, plane);  in g4x_compute_wm0()
794 			     int plane,  in g4x_compute_srwm()  argument
813 	crtc = intel_get_crtc_for_plane(dev, plane);  in g4x_compute_srwm()
841 #define FW_WM_VLV(value, plane) \  argument
842 	(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
857 		   FW_WM(wm->sr.plane, SR) |  in vlv_write_wm_values()
879 			   FW_WM(wm->sr.plane >> 9, SR_HI) |  in vlv_write_wm_values()
894 			   FW_WM(wm->sr.plane >> 9, SR_HI) |  in vlv_write_wm_values()
911 					 struct drm_plane *plane)  in vlv_compute_drain_latency()  argument
923 	if (!intel_crtc->active || !plane->state->fb)  in vlv_compute_drain_latency()
929 	pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);  in vlv_compute_drain_latency()
952 			  struct intel_plane *plane,  in vlv_compute_wm()  argument
961 	if (!crtc->active || !plane->base.state->fb)  in vlv_compute_wm()
964 	pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);  in vlv_compute_wm()
989 	struct intel_plane *plane;  in vlv_compute_sr_wm()  local
991 	wm->sr.cursor = wm->sr.plane = 0;  in vlv_compute_sr_wm()
1009 	list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {  in vlv_compute_sr_wm()
1010 		if (plane->base.type == DRM_PLANE_TYPE_CURSOR)  in vlv_compute_sr_wm()
1013 		if (plane->pipe != pipe)  in vlv_compute_sr_wm()
1016 		wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),  in vlv_compute_sr_wm()
1017 					      plane, fifo_size);  in vlv_compute_sr_wm()
1018 		if (wm->sr.plane != 0)  in vlv_compute_sr_wm()
1052 		      wm.sr.plane, wm.sr.cursor);  in valleyview_update_wm()
1074 static void valleyview_update_sprite_wm(struct drm_plane *plane,  in valleyview_update_sprite_wm()  argument
1085 	int sprite = to_intel_plane(plane)->plane;  in valleyview_update_sprite_wm()
1091 			vlv_compute_drain_latency(crtc, plane);  in valleyview_update_sprite_wm()
1095 				       to_intel_plane(plane),  in valleyview_update_sprite_wm()
1111 		      wm.sr.plane, wm.sr.cursor);  in valleyview_update_sprite_wm()
1486 	struct intel_plane_wm_parameters plane[I915_MAX_PLANES];  member
2039 	struct drm_plane *plane;  in ilk_compute_wm_parameters()  local
2065 	drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {  in ilk_compute_wm_parameters()
2066 		struct intel_plane *intel_plane = to_intel_plane(plane);  in ilk_compute_wm_parameters()
2597 	int plane;  in skl_ddb_get_hw_state()  local
2601 		for_each_plane(dev_priv, pipe, plane) {  in skl_ddb_get_hw_state()
2602 			val = I915_READ(PLANE_BUF_CFG(pipe, plane));  in skl_ddb_get_hw_state()
2603 			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],  in skl_ddb_get_hw_state()
2628 	int plane;  in skl_get_total_relative_data_rate()  local
2630 	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {  in skl_get_total_relative_data_rate()
2633 		p = &params->plane[plane];  in skl_get_total_relative_data_rate()
2657 	int plane;  in skl_allocate_pipe_ddb()  local
2662 		memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));  in skl_allocate_pipe_ddb()
2675 	for_each_plane(dev_priv, pipe, plane) {  in skl_allocate_pipe_ddb()
2678 		p = &params->plane[plane];  in skl_allocate_pipe_ddb()
2682 		minimum[plane] = 8;  in skl_allocate_pipe_ddb()
2683 		alloc_size -= minimum[plane];  in skl_allocate_pipe_ddb()
2695 	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {  in skl_allocate_pipe_ddb()
2700 		p = &params->plane[plane];  in skl_allocate_pipe_ddb()
2710 		plane_blocks = minimum[plane];  in skl_allocate_pipe_ddb()
2714 		ddb->plane[pipe][plane].start = start;  in skl_allocate_pipe_ddb()
2715 		ddb->plane[pipe][plane].end = start + plane_blocks;  in skl_allocate_pipe_ddb()
2785 	if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],  in skl_ddb_allocation_changed()
2786 		   sizeof(new_ddb->plane[pipe])))  in skl_ddb_allocation_changed()
2800 	struct drm_plane *plane;  in skl_compute_wm_global_parameters()  local
2806 	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {  in skl_compute_wm_global_parameters()
2807 		struct intel_plane *intel_plane = to_intel_plane(plane);  in skl_compute_wm_global_parameters()
2820 	struct drm_plane *plane;  in skl_compute_wm_pipe_parameters()  local
2831 			p->plane[0].enabled = true;  in skl_compute_wm_pipe_parameters()
2832 			p->plane[0].bytes_per_pixel = fb->bits_per_pixel / 8;  in skl_compute_wm_pipe_parameters()
2833 			p->plane[0].tiling = fb->modifier[0];  in skl_compute_wm_pipe_parameters()
2835 			p->plane[0].enabled = false;  in skl_compute_wm_pipe_parameters()
2836 			p->plane[0].bytes_per_pixel = 0;  in skl_compute_wm_pipe_parameters()
2837 			p->plane[0].tiling = DRM_FORMAT_MOD_NONE;  in skl_compute_wm_pipe_parameters()
2839 		p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;  in skl_compute_wm_pipe_parameters()
2840 		p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;  in skl_compute_wm_pipe_parameters()
2841 		p->plane[0].rotation = crtc->primary->state->rotation;  in skl_compute_wm_pipe_parameters()
2857 	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {  in skl_compute_wm_pipe_parameters()
2858 		struct intel_plane *intel_plane = to_intel_plane(plane);  in skl_compute_wm_pipe_parameters()
2861 			plane->type == DRM_PLANE_TYPE_OVERLAY)  in skl_compute_wm_pipe_parameters()
2862 			p->plane[i++] = intel_plane->wm;  in skl_compute_wm_pipe_parameters()
2954 		ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);  in skl_compute_wm_level()
2957 						p, &p->plane[i],  in skl_compute_wm_level()
3038 			r->plane[pipe][i][level] = temp;  in skl_compute_wm_results()
3102 					   new->plane[pipe][i][level]);  in skl_write_wm_values()
3114 					    &new->ddb.plane[pipe][i]);  in skl_write_wm_values()
3148 	int plane;  in skl_wm_flush_pipe()  local
3152 	for_each_plane(dev_priv, pipe, plane) {  in skl_wm_flush_pipe()
3153 		I915_WRITE(PLANE_SURF(pipe, plane),  in skl_wm_flush_pipe()
3154 			   I915_READ(PLANE_SURF(pipe, plane)));  in skl_wm_flush_pipe()
3354 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,  in skl_update_sprite_wm()  argument
3358 	struct intel_plane *intel_plane = to_intel_plane(plane);  in skl_update_sprite_wm()
3359 	struct drm_framebuffer *fb = plane->state->fb;  in skl_update_sprite_wm()
3373 	intel_plane->wm.rotation = plane->state->rotation;  in skl_update_sprite_wm()
3425 ilk_update_sprite_wm(struct drm_plane *plane,  in ilk_update_sprite_wm()  argument
3430 	struct drm_device *dev = plane->dev;  in ilk_update_sprite_wm()
3431 	struct intel_plane *intel_plane = to_intel_plane(plane);  in ilk_update_sprite_wm()
3513 			hw->plane[pipe][i][level] =  in skl_pipe_wm_get_hw_state()
3531 			temp = hw->plane[pipe][i][level];  in skl_pipe_wm_get_hw_state()
3678 void intel_update_sprite_watermarks(struct drm_plane *plane,  in intel_update_sprite_watermarks()  argument
3685 	struct drm_i915_private *dev_priv = plane->dev->dev_private;  in intel_update_sprite_watermarks()
3688 		dev_priv->display.update_sprite_wm(plane, crtc,  in intel_update_sprite_watermarks()