Lines Matching refs:CACHELINE_BYTES
217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in intel_emit_post_sync_nonzero_flush()
254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen6_render_ring_flush()
325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen7_render_ring_flush()
408 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen8_render_ring_flush()
1360 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in pc_render_add_request()
1383 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ in pc_render_add_request()
1385 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
1387 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
1389 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
1391 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()
2017 ringbuf->effective_size -= 2 * CACHELINE_BYTES; in intel_init_ring_buffer()
2263 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); in intel_ring_cacheline_align()
2269 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; in intel_ring_cacheline_align()