Lines Matching refs:BIT
104 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { in __intel_display_power_is_enabled()
265 BIT(POWER_DOMAIN_TRANSCODER_A) | \
266 BIT(POWER_DOMAIN_PIPE_B) | \
267 BIT(POWER_DOMAIN_TRANSCODER_B) | \
268 BIT(POWER_DOMAIN_PIPE_C) | \
269 BIT(POWER_DOMAIN_TRANSCODER_C) | \
270 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
271 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
272 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
273 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
274 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
275 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
276 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
277 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
278 BIT(POWER_DOMAIN_AUX_B) | \
279 BIT(POWER_DOMAIN_AUX_C) | \
280 BIT(POWER_DOMAIN_AUX_D) | \
281 BIT(POWER_DOMAIN_AUDIO) | \
282 BIT(POWER_DOMAIN_VGA) | \
283 BIT(POWER_DOMAIN_INIT))
286 BIT(POWER_DOMAIN_PLLS) | \
287 BIT(POWER_DOMAIN_PIPE_A) | \
288 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
289 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
290 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
291 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
292 BIT(POWER_DOMAIN_AUX_A) | \
293 BIT(POWER_DOMAIN_INIT))
295 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
296 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
297 BIT(POWER_DOMAIN_INIT))
299 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
300 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
301 BIT(POWER_DOMAIN_INIT))
303 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
304 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
305 BIT(POWER_DOMAIN_INIT))
307 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
308 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
309 BIT(POWER_DOMAIN_INIT))
320 BIT(POWER_DOMAIN_INIT))
836 for_each_power_well(i, power_well, BIT(domain), power_domains) { in intel_display_power_get()
872 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { in intel_display_power_put()
887 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
890 BIT(POWER_DOMAIN_PIPE_A) | \
891 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
892 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
893 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
894 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
895 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
896 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
897 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
898 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
899 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
900 BIT(POWER_DOMAIN_PORT_CRT) | \
901 BIT(POWER_DOMAIN_PLLS) | \
902 BIT(POWER_DOMAIN_AUX_A) | \
903 BIT(POWER_DOMAIN_AUX_B) | \
904 BIT(POWER_DOMAIN_AUX_C) | \
905 BIT(POWER_DOMAIN_AUX_D) | \
906 BIT(POWER_DOMAIN_INIT))
909 BIT(POWER_DOMAIN_INIT))
913 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
916 BIT(POWER_DOMAIN_INIT))
918 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
922 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
923 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
924 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
925 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
926 BIT(POWER_DOMAIN_PORT_CRT) | \
927 BIT(POWER_DOMAIN_AUX_B) | \
928 BIT(POWER_DOMAIN_AUX_C) | \
929 BIT(POWER_DOMAIN_INIT))
932 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
933 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
934 BIT(POWER_DOMAIN_AUX_B) | \
935 BIT(POWER_DOMAIN_INIT))
938 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
939 BIT(POWER_DOMAIN_AUX_B) | \
940 BIT(POWER_DOMAIN_INIT))
943 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
944 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
945 BIT(POWER_DOMAIN_AUX_C) | \
946 BIT(POWER_DOMAIN_INIT))
949 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
950 BIT(POWER_DOMAIN_AUX_C) | \
951 BIT(POWER_DOMAIN_INIT))
954 BIT(POWER_DOMAIN_PIPE_A) | \
955 BIT(POWER_DOMAIN_INIT))
958 BIT(POWER_DOMAIN_PIPE_B) | \
959 BIT(POWER_DOMAIN_INIT))
962 BIT(POWER_DOMAIN_PIPE_C) | \
963 BIT(POWER_DOMAIN_INIT))
966 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
967 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
968 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
969 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
970 BIT(POWER_DOMAIN_AUX_B) | \
971 BIT(POWER_DOMAIN_AUX_C) | \
972 BIT(POWER_DOMAIN_INIT))
975 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
976 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
977 BIT(POWER_DOMAIN_AUX_D) | \
978 BIT(POWER_DOMAIN_INIT))
981 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
982 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
983 BIT(POWER_DOMAIN_AUX_D) | \
984 BIT(POWER_DOMAIN_INIT))
987 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
988 BIT(POWER_DOMAIN_AUX_D) | \
989 BIT(POWER_DOMAIN_INIT))