73 	return I915_READ(HSW_PWR_WELL_DRIVER) ==  in hsw_power_well_enabled()
238 	tmp = I915_READ(HSW_PWR_WELL_DRIVER);  in hsw_set_power_well()
249 			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &  in hsw_set_power_well()
329 	tmp = I915_READ(HSW_PWR_WELL_DRIVER);  in skl_set_power_well()
330 	fuse_status = I915_READ(SKL_FUSE_STATUS);  in skl_set_power_well()
334 		if (wait_for((I915_READ(SKL_FUSE_STATUS) &  in skl_set_power_well()
369 			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &  in skl_set_power_well()
385 			if (wait_for((I915_READ(SKL_FUSE_STATUS) &  in skl_set_power_well()
389 			if (wait_for((I915_READ(SKL_FUSE_STATUS) &  in skl_set_power_well()
408 	if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)  in hsw_power_well_sync_hw()
430 	return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;  in skl_power_well_enabled()
602 	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |  in vlv_dpio_cmn_power_well_enable()
619 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);  in vlv_dpio_cmn_power_well_enable()
633 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);  in vlv_dpio_cmn_power_well_disable()
653 		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |  in chv_dpio_cmn_power_well_enable()
655 		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |  in chv_dpio_cmn_power_well_enable()
659 		I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |  in chv_dpio_cmn_power_well_enable()
666 	if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))  in chv_dpio_cmn_power_well_enable()
669 	I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |  in chv_dpio_cmn_power_well_enable()
690 	I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &  in chv_dpio_cmn_power_well_disable()
1414 	    I915_READ(DPIO_CTL) & DPIO_CMNRST)  in vlv_cmnlane_wa()