157 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)  in AXXX_CP_RB_CNTL_BUFSZ()  argument
159 	return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;  in AXXX_CP_RB_CNTL_BUFSZ()
163 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)  in AXXX_CP_RB_CNTL_BLKSZ()  argument
165 	return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;  in AXXX_CP_RB_CNTL_BLKSZ()
169 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)  in AXXX_CP_RB_CNTL_BUF_SWAP()  argument
171 	return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;  in AXXX_CP_RB_CNTL_BUF_SWAP()
180 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)  in AXXX_CP_RB_RPTR_ADDR_SWAP()  argument
182 	return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;  in AXXX_CP_RB_RPTR_ADDR_SWAP()
186 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)  in AXXX_CP_RB_RPTR_ADDR_ADDR()  argument
188 	return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;  in AXXX_CP_RB_RPTR_ADDR_ADDR()
204 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START()  argument
206 …return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1…  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START()
210 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START()  argument
212 …return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2…  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START()
216 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START()  argument
218 …return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_S…  in AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START()
224 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)  in AXXX_CP_MEQ_THRESHOLDS_MEQ_END()  argument
226 	return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;  in AXXX_CP_MEQ_THRESHOLDS_MEQ_END()
230 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)  in AXXX_CP_MEQ_THRESHOLDS_ROQ_END()  argument
232 	return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;  in AXXX_CP_MEQ_THRESHOLDS_ROQ_END()
238 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)  in AXXX_CP_CSQ_AVAIL_RING()  argument
240 	return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;  in AXXX_CP_CSQ_AVAIL_RING()
244 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)  in AXXX_CP_CSQ_AVAIL_IB1()  argument
246 	return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;  in AXXX_CP_CSQ_AVAIL_IB1()
250 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)  in AXXX_CP_CSQ_AVAIL_IB2()  argument
252 	return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;  in AXXX_CP_CSQ_AVAIL_IB2()
258 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)  in AXXX_CP_STQ_AVAIL_ST()  argument
260 	return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;  in AXXX_CP_STQ_AVAIL_ST()
266 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)  in AXXX_CP_MEQ_AVAIL_MEQ()  argument
268 	return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;  in AXXX_CP_MEQ_AVAIL_MEQ()
274 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)  in AXXX_SCRATCH_UMSK_UMSK()  argument
276 	return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;  in AXXX_SCRATCH_UMSK_UMSK()
280 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)  in AXXX_SCRATCH_UMSK_SWAP()  argument
282 	return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;  in AXXX_SCRATCH_UMSK_SWAP()
324 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)  in AXXX_CP_CSQ_RB_STAT_RPTR()  argument
326 	return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;  in AXXX_CP_CSQ_RB_STAT_RPTR()
330 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)  in AXXX_CP_CSQ_RB_STAT_WPTR()  argument
332 	return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;  in AXXX_CP_CSQ_RB_STAT_WPTR()
338 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)  in AXXX_CP_CSQ_IB1_STAT_RPTR()  argument
340 	return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;  in AXXX_CP_CSQ_IB1_STAT_RPTR()
344 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)  in AXXX_CP_CSQ_IB1_STAT_WPTR()  argument
346 	return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;  in AXXX_CP_CSQ_IB1_STAT_WPTR()
352 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)  in AXXX_CP_CSQ_IB2_STAT_RPTR()  argument
354 	return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;  in AXXX_CP_CSQ_IB2_STAT_RPTR()
358 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)  in AXXX_CP_CSQ_IB2_STAT_WPTR()  argument
360 	return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;  in AXXX_CP_CSQ_IB2_STAT_WPTR()