260 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)  in dsi_write()  function
634 	dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);  in dsi_phy_sw_reset()
638 	dsi_write(msm_host, REG_DSI_PHY_RESET, 0);  in dsi_phy_sw_reset()
657 	dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);  in dsi_intr_ctrl()
703 		dsi_write(msm_host, REG_DSI_CTRL, 0);  in dsi_ctrl_config()
724 		dsi_write(msm_host, REG_DSI_VID_CFG0, data);  in dsi_ctrl_config()
728 		dsi_write(msm_host, REG_DSI_VID_CFG1, 0);  in dsi_ctrl_config()
733 		dsi_write(msm_host, REG_DSI_CMD_CFG0, data);  in dsi_ctrl_config()
740 		dsi_write(msm_host, REG_DSI_CMD_CFG1, data);  in dsi_ctrl_config()
743 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,  in dsi_ctrl_config()
756 	dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);  in dsi_ctrl_config()
760 	dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);  in dsi_ctrl_config()
765 	dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);  in dsi_ctrl_config()
768 	dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);  in dsi_ctrl_config()
772 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_ctrl_config()
780 		dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,  in dsi_ctrl_config()
787 		dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,  in dsi_ctrl_config()
792 	dsi_write(msm_host, REG_DSI_CTRL, data);  in dsi_ctrl_config()
812 		dsi_write(msm_host, REG_DSI_ACTIVE_H,  in dsi_timing_setup()
815 		dsi_write(msm_host, REG_DSI_ACTIVE_V,  in dsi_timing_setup()
818 		dsi_write(msm_host, REG_DSI_TOTAL,  in dsi_timing_setup()
822 		dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,  in dsi_timing_setup()
825 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);  in dsi_timing_setup()
826 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,  in dsi_timing_setup()
833 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,  in dsi_timing_setup()
840 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,  in dsi_timing_setup()
848 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset()
851 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset()
853 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset()
878 	dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);  in dsi_op_mode_config()
892 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);  in dsi_set_tx_power_mode()
1187 	dsi_write(msm_host, REG_DSI_CTRL, data1);  in dsi_sw_reset_restore()
1194 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset_restore()
1198 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset_restore()
1200 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset_restore()
1202 	dsi_write(msm_host, REG_DSI_CTRL, data0);  in dsi_sw_reset_restore()
1230 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);  in dsi_ack_err_status()
1232 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);  in dsi_ack_err_status()
1244 		dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);  in dsi_timeout_status()
1256 		dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);  in dsi_dln0_phy_err()
1269 		dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);  in dsi_fifo_status()
1284 		dsi_write(msm_host, REG_DSI_STATUS0, status);  in dsi_status()
1297 		dsi_write(msm_host, REG_DSI_CLK_STATUS, status);  in dsi_clk_status()
1328 	dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);  in dsi_host_irq()
1648 	dsi_write(msm_host, REG_DSI_CTRL,  in msm_dsi_host_xfer_prepare()
1663 	dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);  in msm_dsi_host_xfer_restore()
1729 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,  in msm_dsi_host_cmd_rx()
1732 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);  in msm_dsi_host_cmd_rx()
1819 	dsi_write(msm_host, REG_DSI_DMA_BASE, iova);  in msm_dsi_host_cmd_xfer_commit()
1820 	dsi_write(msm_host, REG_DSI_DMA_LEN, len);  in msm_dsi_host_cmd_xfer_commit()
1821 	dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);  in msm_dsi_host_cmd_xfer_commit()