112 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)  in MDP4_VERSION_MINOR()  argument
114 	return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;  in MDP4_VERSION_MINOR()
118 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)  in MDP4_VERSION_MAJOR()  argument
120 	return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;  in MDP4_VERSION_MAJOR()
140 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_PRIM()  argument
142 	return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;  in MDP4_DISP_INTF_SEL_PRIM()
146 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_SEC()  argument
148 	return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;  in MDP4_DISP_INTF_SEL_SEC()
152 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_EXT()  argument
154 	return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;  in MDP4_DISP_INTF_SEL_EXT()
182 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE0()  argument
184 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
189 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE1()  argument
191 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
196 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE2()  argument
198 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
203 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE3()  argument
205 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
210 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE4()  argument
212 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
217 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE5()  argument
219 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE5()
224 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE6()  argument
226 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE6()
231 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE7()  argument
233 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE7()
242 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE0()  argument
244 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE0()
249 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE1()  argument
251 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE1()
256 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE2()  argument
258 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE2()
263 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE3()  argument
265 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE3()
270 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE4()  argument
272 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE4()
277 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE5()  argument
279 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE5()
284 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE6()  argument
286 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE6()
291 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE7()  argument
293 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE7()
325 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)  in MDP4_OVLP_SIZE_HEIGHT()  argument
327 	return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;  in MDP4_OVLP_SIZE_HEIGHT()
331 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)  in MDP4_OVLP_SIZE_WIDTH()  argument
333 	return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;  in MDP4_OVLP_SIZE_WIDTH()
357 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_FG_ALPHA()  argument
359 	return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;  in MDP4_OVLP_STAGE_OP_FG_ALPHA()
365 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_BG_ALPHA()  argument
367 	return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;  in MDP4_OVLP_STAGE_OP_BG_ALPHA()
460 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_G_BPC()  argument
462 	return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;  in MDP4_DMA_CONFIG_G_BPC()
466 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_B_BPC()  argument
468 	return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;  in MDP4_DMA_CONFIG_B_BPC()
472 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_R_BPC()  argument
474 	return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;  in MDP4_DMA_CONFIG_R_BPC()
479 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)  in MDP4_DMA_CONFIG_PACK()  argument
481 	return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;  in MDP4_DMA_CONFIG_PACK()
489 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_SRC_SIZE_HEIGHT()  argument
491 	return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;  in MDP4_DMA_SRC_SIZE_HEIGHT()
495 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_SRC_SIZE_WIDTH()  argument
497 	return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;  in MDP4_DMA_SRC_SIZE_WIDTH()
507 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_DST_SIZE_HEIGHT()  argument
509 	return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;  in MDP4_DMA_DST_SIZE_HEIGHT()
513 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_DST_SIZE_WIDTH()  argument
515 	return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;  in MDP4_DMA_DST_SIZE_WIDTH()
521 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_WIDTH()  argument
523 	return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;  in MDP4_DMA_CURSOR_SIZE_WIDTH()
527 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_HEIGHT()  argument
529 	return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;  in MDP4_DMA_CURSOR_SIZE_HEIGHT()
537 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)  in MDP4_DMA_CURSOR_POS_X()  argument
539 	return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;  in MDP4_DMA_CURSOR_POS_X()
543 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)  in MDP4_DMA_CURSOR_POS_Y()  argument
545 	return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;  in MDP4_DMA_CURSOR_POS_Y()
552 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)  in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()  argument
554 …return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT…  in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()
594 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_SRC_SIZE_HEIGHT()  argument
596 	return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;  in MDP4_PIPE_SRC_SIZE_HEIGHT()
600 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_SRC_SIZE_WIDTH()  argument
602 	return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;  in MDP4_PIPE_SRC_SIZE_WIDTH()
608 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)  in MDP4_PIPE_SRC_XY_Y()  argument
610 	return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;  in MDP4_PIPE_SRC_XY_Y()
614 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)  in MDP4_PIPE_SRC_XY_X()  argument
616 	return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;  in MDP4_PIPE_SRC_XY_X()
622 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_DST_SIZE_HEIGHT()  argument
624 	return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;  in MDP4_PIPE_DST_SIZE_HEIGHT()
628 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_DST_SIZE_WIDTH()  argument
630 	return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;  in MDP4_PIPE_DST_SIZE_WIDTH()
636 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)  in MDP4_PIPE_DST_XY_Y()  argument
638 	return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;  in MDP4_PIPE_DST_XY_Y()
642 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)  in MDP4_PIPE_DST_XY_X()  argument
644 	return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;  in MDP4_PIPE_DST_XY_X()
658 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P0()  argument
660 	return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;  in MDP4_PIPE_SRC_STRIDE_A_P0()
664 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P1()  argument
666 	return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;  in MDP4_PIPE_SRC_STRIDE_A_P1()
672 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P2()  argument
674 	return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;  in MDP4_PIPE_SRC_STRIDE_B_P2()
678 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P3()  argument
680 	return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;  in MDP4_PIPE_SRC_STRIDE_B_P3()
686 static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_FRAME_SIZE_HEIGHT()  argument
688 	return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK;  in MDP4_PIPE_FRAME_SIZE_HEIGHT()
692 static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_FRAME_SIZE_WIDTH()  argument
694 	return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK;  in MDP4_PIPE_FRAME_SIZE_WIDTH()
700 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_G_BPC()  argument
702 	return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_G_BPC()
706 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_B_BPC()  argument
708 	return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_B_BPC()
712 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_R_BPC()  argument
714 	return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_R_BPC()
718 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP4_PIPE_SRC_FORMAT_A_BPC()  argument
720 	return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_A_BPC()
725 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_CPP()  argument
727 	return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;  in MDP4_PIPE_SRC_FORMAT_CPP()
732 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()  argument
734 …return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MA…  in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()
740 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()  argument
742 …return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MA…  in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()
747 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()  argument
749 	return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;  in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()
753 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)  in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()  argument
755 …return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MA…  in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()
761 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM0()  argument
763 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM0()
767 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM1()  argument
769 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM1()
773 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM2()  argument
775 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM2()
779 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM3()  argument
781 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM3()
789 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()  argument
791 …return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MA…  in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()
795 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()  argument
797 …return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MA…  in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()
847 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PULSEW()  argument
849 	return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;  in MDP4_LCDC_HSYNC_CTRL_PULSEW()
853 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PERIOD()  argument
855 	return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;  in MDP4_LCDC_HSYNC_CTRL_PERIOD()
865 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_START()  argument
867 	return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;  in MDP4_LCDC_DISPLAY_HCTRL_START()
871 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_END()  argument
873 	return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;  in MDP4_LCDC_DISPLAY_HCTRL_END()
883 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_START()  argument
885 	return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;  in MDP4_LCDC_ACTIVE_HCTL_START()
889 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_END()  argument
891 	return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;  in MDP4_LCDC_ACTIVE_HCTL_END()
904 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_LCDC_UNDERFLOW_CLR_COLOR()  argument
906 	return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;  in MDP4_LCDC_UNDERFLOW_CLR_COLOR()
942 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()  argument
944 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()
948 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()  argument
950 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()
954 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()  argument
956 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()
960 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()  argument
962 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()
968 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()  argument
970 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__…  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()
974 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()  argument
976 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__…  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()
980 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()  argument
982 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__…  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()
1021 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PULSEW()  argument
1023 	return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;  in MDP4_DTV_HSYNC_CTRL_PULSEW()
1027 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PERIOD()  argument
1029 	return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;  in MDP4_DTV_HSYNC_CTRL_PERIOD()
1039 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_START()  argument
1041 	return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;  in MDP4_DTV_DISPLAY_HCTRL_START()
1045 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_END()  argument
1047 	return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;  in MDP4_DTV_DISPLAY_HCTRL_END()
1057 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_START()  argument
1059 	return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;  in MDP4_DTV_ACTIVE_HCTL_START()
1063 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_END()  argument
1065 	return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;  in MDP4_DTV_ACTIVE_HCTL_END()
1078 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DTV_UNDERFLOW_CLR_COLOR()  argument
1080 	return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;  in MDP4_DTV_UNDERFLOW_CLR_COLOR()
1100 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PULSEW()  argument
1102 	return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;  in MDP4_DSI_HSYNC_CTRL_PULSEW()
1106 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PERIOD()  argument
1108 	return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;  in MDP4_DSI_HSYNC_CTRL_PERIOD()
1118 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_START()  argument
1120 	return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;  in MDP4_DSI_DISPLAY_HCTRL_START()
1124 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_END()  argument
1126 	return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;  in MDP4_DSI_DISPLAY_HCTRL_END()
1136 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_START()  argument
1138 	return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;  in MDP4_DSI_ACTIVE_HCTL_START()
1142 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_END()  argument
1144 	return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;  in MDP4_DSI_ACTIVE_HCTL_END()
1157 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DSI_UNDERFLOW_CLR_COLOR()  argument
1159 	return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;  in MDP4_DSI_UNDERFLOW_CLR_COLOR()