Lines Matching refs:i0
184 static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); } in REG_MDP5_MDP() argument
186 static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0);… in REG_MDP5_MDP_HW_VERSION() argument
206 …tic inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i0)… in REG_MDP5_MDP_DISP_INTF_SEL() argument
232 static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); } in REG_MDP5_MDP_INTR_EN() argument
234 static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0)… in REG_MDP5_MDP_INTR_STATUS() argument
236 static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0);… in REG_MDP5_MDP_INTR_CLEAR() argument
238 static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0… in REG_MDP5_MDP_HIST_INTR_EN() argument
240 … inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MDP(i0)… in REG_MDP5_MDP_HIST_INTR_STATUS() argument
242 …c inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP(i0)… in REG_MDP5_MDP_HIST_INTR_CLEAR() argument
244 static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); } in REG_MDP5_MDP_SPARE_0() argument
247 …nline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_M… in REG_MDP5_MDP_SMP_ALLOC_W() argument
249 …e uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_M… in REG_MDP5_MDP_SMP_ALLOC_W_REG() argument
269 …nline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_M… in REG_MDP5_MDP_SMP_ALLOC_R() argument
271 …e uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_M… in REG_MDP5_MDP_SMP_ALLOC_R_REG() argument
301 …c inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __off… in REG_MDP5_MDP_IGC() argument
303 …int32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 … in REG_MDP5_MDP_IGC_LUT() argument
305 …2_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 … in REG_MDP5_MDP_IGC_LUT_REG() argument
342 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } in REG_MDP5_CTL() argument
356 …atic inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER() argument
358 … inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER_REG() argument
422 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); } in REG_MDP5_CTL_OP() argument
444 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); } in REG_MDP5_CTL_FLUSH() argument
475 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); } in REG_MDP5_CTL_START() argument
477 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); } in REG_MDP5_CTL_PACK_3D() argument
495 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } in REG_MDP5_PIPE() argument
497 …c inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0)… in REG_MDP5_PIPE_OP_MODE() argument
512 …ne uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0)… in REG_MDP5_PIPE_HIST_CTL_BASE() argument
514 …ne uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0)… in REG_MDP5_PIPE_HIST_LUT_BASE() argument
516 …ne uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0)… in REG_MDP5_PIPE_HIST_LUT_SWAP() argument
518 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0() argument
532 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1() argument
546 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2() argument
560 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3() argument
574 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4() argument
582 …2_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument
584 …REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument
598 …_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument
600 …EG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument
614 …32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument
616 … REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument
624 …2_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_BIAS() argument
626 …REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument
634 … inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_SIZE() argument
648 …ine uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_IMG_SIZE() argument
662 …ic inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_XY() argument
676 … inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0)… in REG_MDP5_PIPE_OUT_SIZE() argument
690 …ic inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0)… in REG_MDP5_PIPE_OUT_XY() argument
704 …inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC0_ADDR() argument
706 …inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC1_ADDR() argument
708 …inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC2_ADDR() argument
710 …inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC3_ADDR() argument
712 …ine uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_STRIDE_A() argument
726 …ine uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_STRIDE_B() argument
740 …uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0)… in REG_MDP5_PIPE_STILE_FRAME_SIZE() argument
742 …nline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_FORMAT() argument
796 …nline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_UNPACK() argument
822 …line uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_OP_MODE() argument
838 …nt32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_CONSTANT_COLOR() argument
840 …ine uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0)… in REG_MDP5_PIPE_FETCH_CONFIG() argument
842 …inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0)… in REG_MDP5_PIPE_VC1_RANGE() argument
844 …int32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0)… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0() argument
846 …int32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0)… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1() argument
848 …int32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0)… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2() argument
850 …nt32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS() argument
852 …int32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC0_ADDR() argument
854 …int32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC1_ADDR() argument
856 …int32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC2_ADDR() argument
858 …int32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC3_ADDR() argument
860 …nline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0)… in REG_MDP5_PIPE_DECIMATION() argument
874 …ine uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_CONFIG() argument
914 …nt32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_PHASE_STEP_X() argument
916 …nt32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y() argument
918 …2_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X() argument
920 …2_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y() argument
922 …nt32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_INIT_PHASE_X() argument
924 …nt32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y() argument
938 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } in REG_MDP5_LM() argument
940 …ic inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0);… in REG_MDP5_LM_BLEND_COLOR_OUT() argument
946 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); } in REG_MDP5_LM_OUT_SIZE() argument
960 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0… in REG_MDP5_LM_BORDER_COLOR_0() argument
962 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0… in REG_MDP5_LM_BORDER_COLOR_1() argument
964 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_L… in REG_MDP5_LM_BLEND() argument
966 …nline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_… in REG_MDP5_LM_BLEND_OP_MODE() argument
988 …line uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_… in REG_MDP5_LM_BLEND_FG_ALPHA() argument
990 …line uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_… in REG_MDP5_LM_BLEND_BG_ALPHA() argument
992 …int32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000002c + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument
994 …int32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000030 + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument
996 …nt32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000034 + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument
998 …nt32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000038 + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument
1000 …int32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000003c + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument
1002 …int32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000040 + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument
1004 …nt32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000044 + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument
1006 …nt32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000048 + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument
1008 …ic inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_IMG_SIZE() argument
1022 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); } in REG_MDP5_LM_CURSOR_SIZE() argument
1036 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); } in REG_MDP5_LM_CURSOR_XY() argument
1050 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0)… in REG_MDP5_LM_CURSOR_STRIDE() argument
1058 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0)… in REG_MDP5_LM_CURSOR_FORMAT() argument
1066 …c inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BASE_ADDR() argument
1068 …ic inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_START_XY() argument
1082 …nline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_CONFIG() argument
1092 …inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_PARAM() argument
1094 … uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0() argument
1096 … uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1() argument
1098 …uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0() argument
1100 …uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1() argument
1102 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); } in REG_MDP5_LM_GC_LUT_BASE() argument
1114 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP() argument
1116 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP_OP_MODE() argument
1133 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);… in REG_MDP5_DSPP_PCC_BASE() argument
1135 …ic inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0)… in REG_MDP5_DSPP_DITHER_DEPTH() argument
1137 …c inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0)… in REG_MDP5_DSPP_HIST_CTL_BASE() argument
1139 …c inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0)… in REG_MDP5_DSPP_HIST_LUT_BASE() argument
1141 …c inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0)… in REG_MDP5_DSPP_HIST_LUT_SWAP() argument
1143 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); } in REG_MDP5_DSPP_PA_BASE() argument
1145 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0… in REG_MDP5_DSPP_GAMUT_BASE() argument
1147 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); } in REG_MDP5_DSPP_GC_BASE() argument
1159 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } in REG_MDP5_PP() argument
1161 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0)… in REG_MDP5_PP_TEAR_CHECK_EN() argument
1163 … inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0);… in REG_MDP5_PP_SYNC_CONFIG_VSYNC() argument
1173 …inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0);… in REG_MDP5_PP_SYNC_CONFIG_HEIGHT() argument
1175 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0);… in REG_MDP5_PP_SYNC_WRCOUNT() argument
1189 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0… in REG_MDP5_PP_VSYNC_INIT_VAL() argument
1191 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0)… in REG_MDP5_PP_INT_COUNT_VAL() argument
1205 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); } in REG_MDP5_PP_SYNC_THRESH() argument
1219 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); } in REG_MDP5_PP_START_POS() argument
1221 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); } in REG_MDP5_PP_RD_PTR_IRQ() argument
1223 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); } in REG_MDP5_PP_WR_PTR_IRQ() argument
1225 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0… in REG_MDP5_PP_OUT_LINE_COUNT() argument
1227 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0)… in REG_MDP5_PP_PP_LINE_COUNT() argument
1229 …inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0);… in REG_MDP5_PP_AUTOREFRESH_CONFIG() argument
1231 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); } in REG_MDP5_PP_FBC_MODE() argument
1233 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0… in REG_MDP5_PP_FBC_BUDGET_CTL() argument
1235 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0… in REG_MDP5_PP_FBC_LOSSY_MODE() argument
1248 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF() argument
1250 …nline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0)… in REG_MDP5_INTF_TIMING_ENGINE_EN() argument
1252 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } in REG_MDP5_INTF_CONFIG() argument
1254 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)… in REG_MDP5_INTF_HSYNC_CTL() argument
1268 …inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_PERIOD_F0() argument
1270 …inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_PERIOD_F1() argument
1272 …ic inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_LEN_F0() argument
1274 …ic inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_LEN_F1() argument
1276 …line uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VSTART_F0() argument
1278 …line uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VSTART_F1() argument
1280 …inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VEND_F0() argument
1282 …inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VEND_F1() argument
1284 …nline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VSTART_F0() argument
1293 …nline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VSTART_F1() argument
1301 … inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VEND_F0() argument
1303 … inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VEND_F1() argument
1305 …ic inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_HCTL() argument
1319 …tic inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_HCTL() argument
1334 …ic inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0)… in REG_MDP5_INTF_BORDER_COLOR() argument
1336 …inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0)… in REG_MDP5_INTF_UNDERFLOW_COLOR() argument
1338 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0… in REG_MDP5_INTF_HSYNC_SKEW() argument
1340 …ic inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0)… in REG_MDP5_INTF_POLARITY_CTL() argument
1345 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0);… in REG_MDP5_INTF_TEST_CTL() argument
1347 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0)… in REG_MDP5_INTF_TP_COLOR0() argument
1349 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0)… in REG_MDP5_INTF_TP_COLOR1() argument
1351 …int32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0)… in REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN() argument
1353 …ic inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0)… in REG_MDP5_INTF_PANEL_FORMAT() argument
1355 …ne uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0)… in REG_MDP5_INTF_FRAME_LINE_COUNT_EN() argument
1357 …tic inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0)… in REG_MDP5_INTF_FRAME_COUNT() argument
1359 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0… in REG_MDP5_INTF_LINE_COUNT() argument
1361 …nline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0)… in REG_MDP5_INTF_DEFLICKER_CONFIG() argument
1363 … uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0)… in REG_MDP5_INTF_DEFLICKER_STRNG_COEFF() argument
1365 …e uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0)… in REG_MDP5_INTF_DEFLICKER_WEAK_COEFF() argument
1367 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0… in REG_MDP5_INTF_TPG_ENABLE() argument
1369 …nline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_MAIN_CONTROL() argument
1371 …nline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_VIDEO_CONFIG() argument
1373 …e uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_COMPONENT_LIMITS() argument
1375 …c inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_RECTANGLE() argument
1377 …line uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_INITIAL_VALUE() argument
1379 …2_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME() argument
1381 …inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_RGB_MAPPING() argument
1391 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } in REG_MDP5_AD() argument
1393 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } in REG_MDP5_AD_BYPASS() argument
1395 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); } in REG_MDP5_AD_CTRL_0() argument
1397 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); } in REG_MDP5_AD_CTRL_1() argument
1399 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); } in REG_MDP5_AD_FRAME_SIZE() argument
1401 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); } in REG_MDP5_AD_CON_CTRL_0() argument
1403 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); } in REG_MDP5_AD_CON_CTRL_1() argument
1405 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); } in REG_MDP5_AD_STR_MAN() argument
1407 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); } in REG_MDP5_AD_VAR() argument
1409 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); } in REG_MDP5_AD_DITH() argument
1411 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); } in REG_MDP5_AD_DITH_CTRL() argument
1413 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); } in REG_MDP5_AD_AMP_LIM() argument
1415 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); } in REG_MDP5_AD_SLOPE() argument
1417 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); } in REG_MDP5_AD_BW_LVL() argument
1419 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); } in REG_MDP5_AD_LOGO_POS() argument
1421 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); } in REG_MDP5_AD_LUT_FI() argument
1423 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); } in REG_MDP5_AD_LUT_CC() argument
1425 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); } in REG_MDP5_AD_STR_LIM() argument
1427 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); } in REG_MDP5_AD_CALIB_AB() argument
1429 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); } in REG_MDP5_AD_CALIB_CD() argument
1431 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); } in REG_MDP5_AD_MODE_SEL() argument
1433 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); } in REG_MDP5_AD_TFILT_CTRL() argument
1435 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); } in REG_MDP5_AD_BL_MINMAX() argument
1437 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); } in REG_MDP5_AD_BL() argument
1439 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); } in REG_MDP5_AD_BL_MAX() argument
1441 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); } in REG_MDP5_AD_AL() argument
1443 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); } in REG_MDP5_AD_AL_MIN() argument
1445 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); } in REG_MDP5_AD_AL_FILT() argument
1447 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); } in REG_MDP5_AD_CFG_BUF() argument
1449 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); } in REG_MDP5_AD_LUT_AL() argument
1451 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); } in REG_MDP5_AD_TARG_STR() argument
1453 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); } in REG_MDP5_AD_START_CALC() argument
1455 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); } in REG_MDP5_AD_STR_OUT() argument
1457 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); } in REG_MDP5_AD_BL_OUT() argument
1459 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); } in REG_MDP5_AD_CALC_DONE() argument