31 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)  in crtc_wr_cio_state()  argument
33 	NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,  in crtc_wr_cio_state()
43 	struct drm_crtc *crtc = &nv_crtc->base;  in nv04_cursor_set_offset()  local
50 	if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)  in nv04_cursor_set_offset()
55 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);  in nv04_cursor_set_offset()
56 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);  in nv04_cursor_set_offset()
57 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);  in nv04_cursor_set_offset()
63 nv04_cursor_init(struct nouveau_crtc *crtc)  in nv04_cursor_init()  argument
65 	crtc->cursor.set_offset = nv04_cursor_set_offset;  in nv04_cursor_init()
66 	crtc->cursor.set_pos = nv04_cursor_set_pos;  in nv04_cursor_init()
67 	crtc->cursor.hide = nv04_cursor_hide;  in nv04_cursor_init()
68 	crtc->cursor.show = nv04_cursor_show;  in nv04_cursor_init()