Lines Matching refs:priv
58 struct nv04_fifo_priv *priv = (void *)parent->engine; in nv04_fifo_object_attach() local
86 mutex_lock(&nv_subdev(priv)->mutex); in nv04_fifo_object_attach()
87 ret = nvkm_ramht_insert(priv->ramht, chid, handle, context); in nv04_fifo_object_attach()
88 mutex_unlock(&nv_subdev(priv)->mutex); in nv04_fifo_object_attach()
95 struct nv04_fifo_priv *priv = (void *)parent->engine; in nv04_fifo_object_detach() local
96 mutex_lock(&nv_subdev(priv)->mutex); in nv04_fifo_object_detach()
97 nvkm_ramht_remove(priv->ramht, cookie); in nv04_fifo_object_detach()
98 mutex_unlock(&nv_subdev(priv)->mutex); in nv04_fifo_object_detach()
118 struct nv04_fifo_priv *priv = (void *)engine; in nv04_fifo_chan_ctor() local
146 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv04_fifo_chan_ctor()
147 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv04_fifo_chan_ctor()
148 nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); in nv04_fifo_chan_ctor()
149 nv_wo32(priv->ramfc, chan->ramfc + 0x10, in nv04_fifo_chan_ctor()
162 struct nv04_fifo_priv *priv = (void *)object->engine; in nv04_fifo_chan_dtor() local
164 struct ramfc_desc *c = priv->ramfc_desc; in nv04_fifo_chan_dtor()
167 nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000); in nv04_fifo_chan_dtor()
176 struct nv04_fifo_priv *priv = (void *)object->engine; in nv04_fifo_chan_init() local
186 spin_lock_irqsave(&priv->base.lock, flags); in nv04_fifo_chan_init()
187 nv_mask(priv, NV04_PFIFO_MODE, mask, mask); in nv04_fifo_chan_init()
188 spin_unlock_irqrestore(&priv->base.lock, flags); in nv04_fifo_chan_init()
195 struct nv04_fifo_priv *priv = (void *)object->engine; in nv04_fifo_chan_fini() local
197 struct nvkm_gpuobj *fctx = priv->ramfc; in nv04_fifo_chan_fini()
204 spin_lock_irqsave(&priv->base.lock, flags); in nv04_fifo_chan_fini()
205 nv_wr32(priv, NV03_PFIFO_CACHES, 0); in nv04_fifo_chan_fini()
208 chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; in nv04_fifo_chan_fini()
210 nv_mask(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); in nv04_fifo_chan_fini()
211 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 0); in nv04_fifo_chan_fini()
212 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); in nv04_fifo_chan_fini()
214 c = priv->ramfc_desc; in nv04_fifo_chan_fini()
218 u32 rv = (nv_rd32(priv, c->regp) & rm) >> c->regs; in nv04_fifo_chan_fini()
223 c = priv->ramfc_desc; in nv04_fifo_chan_fini()
225 nv_wr32(priv, c->regp, 0x00000000); in nv04_fifo_chan_fini()
228 nv_wr32(priv, NV03_PFIFO_CACHE1_GET, 0); in nv04_fifo_chan_fini()
229 nv_wr32(priv, NV03_PFIFO_CACHE1_PUT, 0); in nv04_fifo_chan_fini()
230 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); in nv04_fifo_chan_fini()
231 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); in nv04_fifo_chan_fini()
232 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_chan_fini()
236 nv_mask(priv, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); in nv04_fifo_chan_fini()
237 nv_wr32(priv, NV03_PFIFO_CACHES, 1); in nv04_fifo_chan_fini()
238 spin_unlock_irqrestore(&priv->base.lock, flags); in nv04_fifo_chan_fini()
302 __acquires(priv->base.lock) in nv04_fifo_pause()
304 struct nv04_fifo_priv *priv = (void *)pfifo; in nv04_fifo_pause() local
307 spin_lock_irqsave(&priv->base.lock, flags); in nv04_fifo_pause()
310 nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000000); in nv04_fifo_pause()
311 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); in nv04_fifo_pause()
322 if (!nv_wait(priv, NV04_PFIFO_CACHE1_PULL0, in nv04_fifo_pause()
324 nv_warn(priv, "timeout idling puller\n"); in nv04_fifo_pause()
326 if (nv_rd32(priv, NV04_PFIFO_CACHE1_PULL0) & in nv04_fifo_pause()
328 nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_pause()
330 nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0x00000000); in nv04_fifo_pause()
335 __releases(priv->base.lock) in nv04_fifo_start()
337 struct nv04_fifo_priv *priv = (void *)pfifo; in nv04_fifo_start() local
340 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); in nv04_fifo_start()
341 nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000001); in nv04_fifo_start()
343 spin_unlock_irqrestore(&priv->base.lock, flags); in nv04_fifo_start()
357 nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) in nv04_fifo_swmthd() argument
367 spin_lock_irqsave(&priv->base.lock, flags); in nv04_fifo_swmthd()
368 if (likely(chid >= priv->base.min && chid <= priv->base.max)) in nv04_fifo_swmthd()
369 chan = (void *)priv->base.channel[chid]; in nv04_fifo_swmthd()
384 nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0); in nv04_fifo_swmthd()
390 engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE); in nv04_fifo_swmthd()
404 spin_unlock_irqrestore(&priv->base.lock, flags); in nv04_fifo_swmthd()
410 struct nv04_fifo_priv *priv, u32 chid, u32 get) in nv04_fifo_cache_error() argument
423 mthd = nv_rd32(priv, NV04_PFIFO_CACHE1_METHOD(ptr)); in nv04_fifo_cache_error()
424 data = nv_rd32(priv, NV04_PFIFO_CACHE1_DATA(ptr)); in nv04_fifo_cache_error()
426 mthd = nv_rd32(priv, NV40_PFIFO_CACHE1_METHOD(ptr)); in nv04_fifo_cache_error()
427 data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr)); in nv04_fifo_cache_error()
430 if (!nv04_fifo_swmthd(priv, chid, mthd, data)) { in nv04_fifo_cache_error()
432 nvkm_client_name_for_fifo_chid(&priv->base, chid); in nv04_fifo_cache_error()
433 nv_error(priv, in nv04_fifo_cache_error()
439 nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0); in nv04_fifo_cache_error()
440 nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_cache_error()
442 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
443 nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1); in nv04_fifo_cache_error()
444 nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); in nv04_fifo_cache_error()
445 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
446 nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1); in nv04_fifo_cache_error()
447 nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0); in nv04_fifo_cache_error()
449 nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, in nv04_fifo_cache_error()
450 nv_rd32(priv, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); in nv04_fifo_cache_error()
451 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_cache_error()
456 struct nv04_fifo_priv *priv, u32 chid) in nv04_fifo_dma_pusher() argument
459 u32 dma_get = nv_rd32(priv, 0x003244); in nv04_fifo_dma_pusher()
460 u32 dma_put = nv_rd32(priv, 0x003240); in nv04_fifo_dma_pusher()
461 u32 push = nv_rd32(priv, 0x003220); in nv04_fifo_dma_pusher()
462 u32 state = nv_rd32(priv, 0x003228); in nv04_fifo_dma_pusher()
464 client_name = nvkm_client_name_for_fifo_chid(&priv->base, chid); in nv04_fifo_dma_pusher()
467 u32 ho_get = nv_rd32(priv, 0x003328); in nv04_fifo_dma_pusher()
468 u32 ho_put = nv_rd32(priv, 0x003320); in nv04_fifo_dma_pusher()
469 u32 ib_get = nv_rd32(priv, 0x003334); in nv04_fifo_dma_pusher()
470 u32 ib_put = nv_rd32(priv, 0x003330); in nv04_fifo_dma_pusher()
472 nv_error(priv, in nv04_fifo_dma_pusher()
478 nv_wr32(priv, 0x003364, 0x00000000); in nv04_fifo_dma_pusher()
480 nv_wr32(priv, 0x003244, dma_put); in nv04_fifo_dma_pusher()
481 nv_wr32(priv, 0x003328, ho_put); in nv04_fifo_dma_pusher()
484 nv_wr32(priv, 0x003334, ib_put); in nv04_fifo_dma_pusher()
486 nv_error(priv, in nv04_fifo_dma_pusher()
492 nv_wr32(priv, 0x003244, dma_put); in nv04_fifo_dma_pusher()
495 nv_wr32(priv, 0x003228, 0x00000000); in nv04_fifo_dma_pusher()
496 nv_wr32(priv, 0x003220, 0x00000001); in nv04_fifo_dma_pusher()
497 nv_wr32(priv, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); in nv04_fifo_dma_pusher()
504 struct nv04_fifo_priv *priv = (void *)subdev; in nv04_fifo_intr() local
505 u32 mask = nv_rd32(priv, NV03_PFIFO_INTR_EN_0); in nv04_fifo_intr()
506 u32 stat = nv_rd32(priv, NV03_PFIFO_INTR_0) & mask; in nv04_fifo_intr()
509 reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1; in nv04_fifo_intr()
510 nv_wr32(priv, NV03_PFIFO_CACHES, 0); in nv04_fifo_intr()
512 chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; in nv04_fifo_intr()
513 get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); in nv04_fifo_intr()
516 nv04_fifo_cache_error(device, priv, chid, get); in nv04_fifo_intr()
521 nv04_fifo_dma_pusher(device, priv, chid); in nv04_fifo_intr()
527 nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); in nv04_fifo_intr()
529 sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); in nv04_fifo_intr()
530 nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); in nv04_fifo_intr()
532 nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); in nv04_fifo_intr()
533 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_intr()
539 nv_wr32(priv, 0x002100, 0x00000010); in nv04_fifo_intr()
543 nv_wr32(priv, 0x002100, 0x40000000); in nv04_fifo_intr()
544 nvkm_fifo_uevent(&priv->base); in nv04_fifo_intr()
550 nv_warn(priv, "unknown intr 0x%08x\n", stat); in nv04_fifo_intr()
551 nv_mask(priv, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); in nv04_fifo_intr()
552 nv_wr32(priv, NV03_PFIFO_INTR_0, stat); in nv04_fifo_intr()
555 nv_wr32(priv, NV03_PFIFO_CACHES, reassign); in nv04_fifo_intr()
564 struct nv04_fifo_priv *priv; in nv04_fifo_ctor() local
567 ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &priv); in nv04_fifo_ctor()
568 *pobject = nv_object(priv); in nv04_fifo_ctor()
572 nvkm_ramht_ref(imem->ramht, &priv->ramht); in nv04_fifo_ctor()
573 nvkm_gpuobj_ref(imem->ramro, &priv->ramro); in nv04_fifo_ctor()
574 nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); in nv04_fifo_ctor()
576 nv_subdev(priv)->unit = 0x00000100; in nv04_fifo_ctor()
577 nv_subdev(priv)->intr = nv04_fifo_intr; in nv04_fifo_ctor()
578 nv_engine(priv)->cclass = &nv04_fifo_cclass; in nv04_fifo_ctor()
579 nv_engine(priv)->sclass = nv04_fifo_sclass; in nv04_fifo_ctor()
580 priv->base.pause = nv04_fifo_pause; in nv04_fifo_ctor()
581 priv->base.start = nv04_fifo_start; in nv04_fifo_ctor()
582 priv->ramfc_desc = nv04_ramfc; in nv04_fifo_ctor()
589 struct nv04_fifo_priv *priv = (void *)object; in nv04_fifo_dtor() local
590 nvkm_gpuobj_ref(NULL, &priv->ramfc); in nv04_fifo_dtor()
591 nvkm_gpuobj_ref(NULL, &priv->ramro); in nv04_fifo_dtor()
592 nvkm_ramht_ref(NULL, &priv->ramht); in nv04_fifo_dtor()
593 nvkm_fifo_destroy(&priv->base); in nv04_fifo_dtor()
599 struct nv04_fifo_priv *priv = (void *)object; in nv04_fifo_init() local
602 ret = nvkm_fifo_init(&priv->base); in nv04_fifo_init()
606 nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff); in nv04_fifo_init()
607 nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); in nv04_fifo_init()
609 nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv04_fifo_init()
610 ((priv->ramht->bits - 9) << 16) | in nv04_fifo_init()
611 (priv->ramht->gpuobj.addr >> 8)); in nv04_fifo_init()
612 nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); in nv04_fifo_init()
613 nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8); in nv04_fifo_init()
615 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); in nv04_fifo_init()
617 nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); in nv04_fifo_init()
618 nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); in nv04_fifo_init()
620 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); in nv04_fifo_init()
621 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_init()
622 nv_wr32(priv, NV03_PFIFO_CACHES, 1); in nv04_fifo_init()