Lines Matching refs:priv
45 gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc) in gf100_gr_zbc_clear_color() argument
47 if (priv->zbc_color[zbc].format) { in gf100_gr_zbc_clear_color()
48 nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
49 nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
50 nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
51 nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
53 nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
54 nv_wr32(priv, 0x405820, zbc); in gf100_gr_zbc_clear_color()
55 nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ in gf100_gr_zbc_clear_color()
59 gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format, in gf100_gr_zbc_color_get() argument
62 struct nvkm_ltc *ltc = nvkm_ltc(priv); in gf100_gr_zbc_color_get()
66 if (priv->zbc_color[i].format) { in gf100_gr_zbc_color_get()
67 if (priv->zbc_color[i].format != format) in gf100_gr_zbc_color_get()
69 if (memcmp(priv->zbc_color[i].ds, ds, sizeof( in gf100_gr_zbc_color_get()
70 priv->zbc_color[i].ds))) in gf100_gr_zbc_color_get()
72 if (memcmp(priv->zbc_color[i].l2, l2, sizeof( in gf100_gr_zbc_color_get()
73 priv->zbc_color[i].l2))) { in gf100_gr_zbc_color_get()
86 memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds)); in gf100_gr_zbc_color_get()
87 memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2)); in gf100_gr_zbc_color_get()
88 priv->zbc_color[zbc].format = format; in gf100_gr_zbc_color_get()
90 gf100_gr_zbc_clear_color(priv, zbc); in gf100_gr_zbc_color_get()
95 gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc) in gf100_gr_zbc_clear_depth() argument
97 if (priv->zbc_depth[zbc].format) in gf100_gr_zbc_clear_depth()
98 nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds); in gf100_gr_zbc_clear_depth()
99 nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format); in gf100_gr_zbc_clear_depth()
100 nv_wr32(priv, 0x405820, zbc); in gf100_gr_zbc_clear_depth()
101 nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ in gf100_gr_zbc_clear_depth()
105 gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format, in gf100_gr_zbc_depth_get() argument
108 struct nvkm_ltc *ltc = nvkm_ltc(priv); in gf100_gr_zbc_depth_get()
112 if (priv->zbc_depth[i].format) { in gf100_gr_zbc_depth_get()
113 if (priv->zbc_depth[i].format != format) in gf100_gr_zbc_depth_get()
115 if (priv->zbc_depth[i].ds != ds) in gf100_gr_zbc_depth_get()
117 if (priv->zbc_depth[i].l2 != l2) { in gf100_gr_zbc_depth_get()
130 priv->zbc_depth[zbc].format = format; in gf100_gr_zbc_depth_get()
131 priv->zbc_depth[zbc].ds = ds; in gf100_gr_zbc_depth_get()
132 priv->zbc_depth[zbc].l2 = l2; in gf100_gr_zbc_depth_get()
134 gf100_gr_zbc_clear_depth(priv, zbc); in gf100_gr_zbc_depth_get()
145 struct gf100_gr_priv *priv = (void *)object->engine; in gf100_fermi_mthd_zbc_color() local
172 ret = gf100_gr_zbc_color_get(priv, args->v0.format, in gf100_fermi_mthd_zbc_color()
191 struct gf100_gr_priv *priv = (void *)object->engine; in gf100_fermi_mthd_zbc_depth() local
200 ret = gf100_gr_zbc_depth_get(priv, args->v0.format, in gf100_fermi_mthd_zbc_depth()
239 struct gf100_gr_priv *priv = (void *)object->engine; in gf100_gr_set_shader_exceptions() local
242 nv_wr32(priv, 0x419e44, data); in gf100_gr_set_shader_exceptions()
243 nv_wr32(priv, 0x419e4c, data); in gf100_gr_set_shader_exceptions()
280 struct gf100_gr_priv *priv = (void *)engine; in gf100_gr_context_ctor() local
281 struct gf100_gr_data *data = priv->mmio_data; in gf100_gr_context_ctor()
282 struct gf100_gr_mmio *mmio = priv->mmio_list; in gf100_gr_context_ctor()
288 priv->size, 0x100, in gf100_gr_context_ctor()
310 for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) { in gf100_gr_context_ctor()
325 for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) { in gf100_gr_context_ctor()
339 for (i = 0; i < priv->size; i += 4) in gf100_gr_context_ctor()
340 nv_wo32(chan, i, priv->data[i / 4]); in gf100_gr_context_ctor()
342 if (!priv->firmware) { in gf100_gr_context_ctor()
638 gf100_gr_zbc_init(struct gf100_gr_priv *priv) in gf100_gr_zbc_init() argument
648 struct nvkm_ltc *ltc = nvkm_ltc(priv); in gf100_gr_zbc_init()
651 if (!priv->zbc_color[0].format) { in gf100_gr_zbc_init()
652 gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]); in gf100_gr_zbc_init()
653 gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]); in gf100_gr_zbc_init()
654 gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]); in gf100_gr_zbc_init()
655 gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]); in gf100_gr_zbc_init()
656 gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000); in gf100_gr_zbc_init()
657 gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000); in gf100_gr_zbc_init()
661 gf100_gr_zbc_clear_color(priv, index); in gf100_gr_zbc_init()
663 gf100_gr_zbc_clear_depth(priv, index); in gf100_gr_zbc_init()
667 gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) in gf100_gr_mmio() argument
676 nv_wr32(priv, addr, init->data); in gf100_gr_mmio()
683 gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) in gf100_gr_icmd() argument
689 nv_wr32(priv, 0x400208, 0x80000000); in gf100_gr_icmd()
696 nv_wr32(priv, 0x400204, init->data); in gf100_gr_icmd()
701 nv_wr32(priv, 0x400200, addr); in gf100_gr_icmd()
702 nv_wait(priv, 0x400700, 0x00000002, 0x00000000); in gf100_gr_icmd()
707 nv_wr32(priv, 0x400208, 0x00000000); in gf100_gr_icmd()
711 gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) in gf100_gr_mthd() argument
723 nv_wr32(priv, 0x40448c, init->data); in gf100_gr_mthd()
728 nv_wr32(priv, 0x404488, ctrl | (addr << 14)); in gf100_gr_mthd()
737 struct gf100_gr_priv *priv = (void *)gr; in gf100_gr_units() local
740 cfg = (u32)priv->gpc_nr; in gf100_gr_units()
741 cfg |= (u32)priv->tpc_total << 8; in gf100_gr_units()
742 cfg |= (u64)priv->rop_nr << 32; in gf100_gr_units()
773 gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc) in gf100_gr_trap_gpc_rop() argument
778 trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); in gf100_gr_trap_gpc_rop()
779 trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); in gf100_gr_trap_gpc_rop()
780 trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); in gf100_gr_trap_gpc_rop()
781 trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); in gf100_gr_trap_gpc_rop()
783 nv_error(priv, "GPC%d/PROP trap:", gpc); in gf100_gr_trap_gpc_rop()
792 nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n", in gf100_gr_trap_gpc_rop()
795 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_trap_gpc_rop()
838 gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc) in gf100_gr_trap_mp() argument
840 u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); in gf100_gr_trap_mp()
841 u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); in gf100_gr_trap_mp()
843 nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc); in gf100_gr_trap_mp()
851 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); in gf100_gr_trap_mp()
852 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr); in gf100_gr_trap_mp()
856 gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc) in gf100_gr_trap_tpc() argument
858 u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508)); in gf100_gr_trap_tpc()
861 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); in gf100_gr_trap_tpc()
862 nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); in gf100_gr_trap_tpc()
863 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); in gf100_gr_trap_tpc()
868 gf100_gr_trap_mp(priv, gpc, tpc); in gf100_gr_trap_tpc()
873 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); in gf100_gr_trap_tpc()
874 nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); in gf100_gr_trap_tpc()
875 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); in gf100_gr_trap_tpc()
880 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); in gf100_gr_trap_tpc()
881 nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); in gf100_gr_trap_tpc()
882 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); in gf100_gr_trap_tpc()
887 nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); in gf100_gr_trap_tpc()
892 gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc) in gf100_gr_trap_gpc() argument
894 u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); in gf100_gr_trap_gpc()
898 gf100_gr_trap_gpc_rop(priv, gpc); in gf100_gr_trap_gpc()
903 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); in gf100_gr_trap_gpc()
904 nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); in gf100_gr_trap_gpc()
905 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); in gf100_gr_trap_gpc()
910 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); in gf100_gr_trap_gpc()
911 nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); in gf100_gr_trap_gpc()
912 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); in gf100_gr_trap_gpc()
917 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); in gf100_gr_trap_gpc()
918 nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); in gf100_gr_trap_gpc()
919 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); in gf100_gr_trap_gpc()
923 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { in gf100_gr_trap_gpc()
926 gf100_gr_trap_tpc(priv, gpc, tpc); in gf100_gr_trap_gpc()
927 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask); in gf100_gr_trap_gpc()
933 nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat); in gf100_gr_trap_gpc()
938 gf100_gr_trap_intr(struct gf100_gr_priv *priv) in gf100_gr_trap_intr() argument
940 u32 trap = nv_rd32(priv, 0x400108); in gf100_gr_trap_intr()
944 u32 stat = nv_rd32(priv, 0x404000); in gf100_gr_trap_intr()
945 nv_error(priv, "DISPATCH 0x%08x\n", stat); in gf100_gr_trap_intr()
946 nv_wr32(priv, 0x404000, 0xc0000000); in gf100_gr_trap_intr()
947 nv_wr32(priv, 0x400108, 0x00000001); in gf100_gr_trap_intr()
952 u32 stat = nv_rd32(priv, 0x404600); in gf100_gr_trap_intr()
953 nv_error(priv, "M2MF 0x%08x\n", stat); in gf100_gr_trap_intr()
954 nv_wr32(priv, 0x404600, 0xc0000000); in gf100_gr_trap_intr()
955 nv_wr32(priv, 0x400108, 0x00000002); in gf100_gr_trap_intr()
960 u32 stat = nv_rd32(priv, 0x408030); in gf100_gr_trap_intr()
961 nv_error(priv, "CCACHE 0x%08x\n", stat); in gf100_gr_trap_intr()
962 nv_wr32(priv, 0x408030, 0xc0000000); in gf100_gr_trap_intr()
963 nv_wr32(priv, 0x400108, 0x00000008); in gf100_gr_trap_intr()
968 u32 stat = nv_rd32(priv, 0x405840); in gf100_gr_trap_intr()
969 nv_error(priv, "SHADER 0x%08x\n", stat); in gf100_gr_trap_intr()
970 nv_wr32(priv, 0x405840, 0xc0000000); in gf100_gr_trap_intr()
971 nv_wr32(priv, 0x400108, 0x00000010); in gf100_gr_trap_intr()
976 u32 stat = nv_rd32(priv, 0x40601c); in gf100_gr_trap_intr()
977 nv_error(priv, "UNK6 0x%08x\n", stat); in gf100_gr_trap_intr()
978 nv_wr32(priv, 0x40601c, 0xc0000000); in gf100_gr_trap_intr()
979 nv_wr32(priv, 0x400108, 0x00000040); in gf100_gr_trap_intr()
984 u32 stat = nv_rd32(priv, 0x404490); in gf100_gr_trap_intr()
985 nv_error(priv, "MACRO 0x%08x\n", stat); in gf100_gr_trap_intr()
986 nv_wr32(priv, 0x404490, 0xc0000000); in gf100_gr_trap_intr()
987 nv_wr32(priv, 0x400108, 0x00000080); in gf100_gr_trap_intr()
992 u32 stat = nv_rd32(priv, 0x407020); in gf100_gr_trap_intr()
994 nv_error(priv, "SKED:"); in gf100_gr_trap_intr()
1004 nv_wr32(priv, 0x407020, 0x40000000); in gf100_gr_trap_intr()
1005 nv_wr32(priv, 0x400108, 0x00000100); in gf100_gr_trap_intr()
1010 u32 stat = nv_rd32(priv, 0x400118); in gf100_gr_trap_intr()
1011 for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { in gf100_gr_trap_intr()
1014 gf100_gr_trap_gpc(priv, gpc); in gf100_gr_trap_intr()
1015 nv_wr32(priv, 0x400118, mask); in gf100_gr_trap_intr()
1019 nv_wr32(priv, 0x400108, 0x01000000); in gf100_gr_trap_intr()
1024 for (rop = 0; rop < priv->rop_nr; rop++) { in gf100_gr_trap_intr()
1025 u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070)); in gf100_gr_trap_intr()
1026 u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144)); in gf100_gr_trap_intr()
1027 nv_error(priv, "ROP%d 0x%08x 0x%08x\n", in gf100_gr_trap_intr()
1029 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); in gf100_gr_trap_intr()
1030 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); in gf100_gr_trap_intr()
1032 nv_wr32(priv, 0x400108, 0x02000000); in gf100_gr_trap_intr()
1037 nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap); in gf100_gr_trap_intr()
1038 nv_wr32(priv, 0x400108, trap); in gf100_gr_trap_intr()
1043 gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base) in gf100_gr_ctxctl_debug_unit() argument
1045 nv_error(priv, "%06x - done 0x%08x\n", base, in gf100_gr_ctxctl_debug_unit()
1046 nv_rd32(priv, base + 0x400)); in gf100_gr_ctxctl_debug_unit()
1047 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, in gf100_gr_ctxctl_debug_unit()
1048 nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), in gf100_gr_ctxctl_debug_unit()
1049 nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); in gf100_gr_ctxctl_debug_unit()
1050 nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, in gf100_gr_ctxctl_debug_unit()
1051 nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), in gf100_gr_ctxctl_debug_unit()
1052 nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c)); in gf100_gr_ctxctl_debug_unit()
1056 gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv) in gf100_gr_ctxctl_debug() argument
1058 u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; in gf100_gr_ctxctl_debug()
1061 gf100_gr_ctxctl_debug_unit(priv, 0x409000); in gf100_gr_ctxctl_debug()
1063 gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); in gf100_gr_ctxctl_debug()
1067 gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv) in gf100_gr_ctxctl_isr() argument
1069 u32 stat = nv_rd32(priv, 0x409c18); in gf100_gr_ctxctl_isr()
1072 u32 code = nv_rd32(priv, 0x409814); in gf100_gr_ctxctl_isr()
1074 u32 class = nv_rd32(priv, 0x409808); in gf100_gr_ctxctl_isr()
1075 u32 addr = nv_rd32(priv, 0x40980c); in gf100_gr_ctxctl_isr()
1078 u32 data = nv_rd32(priv, 0x409810); in gf100_gr_ctxctl_isr()
1080 nv_error(priv, "FECS MTHD subc %d class 0x%04x " in gf100_gr_ctxctl_isr()
1084 nv_wr32(priv, 0x409c20, 0x00000001); in gf100_gr_ctxctl_isr()
1087 nv_error(priv, "FECS ucode error %d\n", code); in gf100_gr_ctxctl_isr()
1092 nv_error(priv, "FECS watchdog timeout\n"); in gf100_gr_ctxctl_isr()
1093 gf100_gr_ctxctl_debug(priv); in gf100_gr_ctxctl_isr()
1094 nv_wr32(priv, 0x409c20, 0x00080000); in gf100_gr_ctxctl_isr()
1099 nv_error(priv, "FECS 0x%08x\n", stat); in gf100_gr_ctxctl_isr()
1100 gf100_gr_ctxctl_debug(priv); in gf100_gr_ctxctl_isr()
1101 nv_wr32(priv, 0x409c20, stat); in gf100_gr_ctxctl_isr()
1112 struct gf100_gr_priv *priv = (void *)subdev; in gf100_gr_intr() local
1113 u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff; in gf100_gr_intr()
1114 u32 stat = nv_rd32(priv, 0x400100); in gf100_gr_intr()
1115 u32 addr = nv_rd32(priv, 0x400704); in gf100_gr_intr()
1118 u32 data = nv_rd32(priv, 0x400708); in gf100_gr_intr()
1119 u32 code = nv_rd32(priv, 0x400110); in gf100_gr_intr()
1123 if (nv_device(priv)->card_type < NV_E0 || subc < 4) in gf100_gr_intr()
1124 class = nv_rd32(priv, 0x404200 + (subc * 4)); in gf100_gr_intr()
1136 nv_wr32(priv, 0x400100, 0x00000001); in gf100_gr_intr()
1143 nv_error(priv, in gf100_gr_intr()
1149 nv_wr32(priv, 0x400100, 0x00000010); in gf100_gr_intr()
1154 nv_error(priv, in gf100_gr_intr()
1158 nv_wr32(priv, 0x400100, 0x00000020); in gf100_gr_intr()
1163 nv_error(priv, "DATA_ERROR ["); in gf100_gr_intr()
1168 nv_wr32(priv, 0x400100, 0x00100000); in gf100_gr_intr()
1173 nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, in gf100_gr_intr()
1175 gf100_gr_trap_intr(priv); in gf100_gr_intr()
1176 nv_wr32(priv, 0x400100, 0x00200000); in gf100_gr_intr()
1181 gf100_gr_ctxctl_isr(priv); in gf100_gr_intr()
1182 nv_wr32(priv, 0x400100, 0x00080000); in gf100_gr_intr()
1187 nv_error(priv, "unknown stat 0x%08x\n", stat); in gf100_gr_intr()
1188 nv_wr32(priv, 0x400100, stat); in gf100_gr_intr()
1191 nv_wr32(priv, 0x400500, 0x00010001); in gf100_gr_intr()
1196 gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base, in gf100_gr_init_fw() argument
1201 nv_wr32(priv, fuc_base + 0x01c0, 0x01000000); in gf100_gr_init_fw()
1203 nv_wr32(priv, fuc_base + 0x01c4, data->data[i]); in gf100_gr_init_fw()
1205 nv_wr32(priv, fuc_base + 0x0180, 0x01000000); in gf100_gr_init_fw()
1208 nv_wr32(priv, fuc_base + 0x0188, i >> 6); in gf100_gr_init_fw()
1209 nv_wr32(priv, fuc_base + 0x0184, code->data[i]); in gf100_gr_init_fw()
1214 nv_wr32(priv, fuc_base + 0x0184, 0); in gf100_gr_init_fw()
1218 gf100_gr_init_csdata(struct gf100_gr_priv *priv, in gf100_gr_init_csdata() argument
1227 nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar); in gf100_gr_init_csdata()
1228 star = nv_rd32(priv, falcon + 0x01c4); in gf100_gr_init_csdata()
1229 temp = nv_rd32(priv, falcon + 0x01c4); in gf100_gr_init_csdata()
1232 nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star); in gf100_gr_init_csdata()
1241 nv_wr32(priv, falcon + 0x01c4, data); in gf100_gr_init_csdata()
1253 nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr); in gf100_gr_init_csdata()
1254 nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar); in gf100_gr_init_csdata()
1255 nv_wr32(priv, falcon + 0x01c4, star + 4); in gf100_gr_init_csdata()
1259 gf100_gr_init_ctxctl(struct gf100_gr_priv *priv) in gf100_gr_init_ctxctl() argument
1261 struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass; in gf100_gr_init_ctxctl()
1262 struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; in gf100_gr_init_ctxctl()
1265 if (priv->firmware) { in gf100_gr_init_ctxctl()
1267 nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); in gf100_gr_init_ctxctl()
1268 gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c, in gf100_gr_init_ctxctl()
1269 &priv->fuc409d); in gf100_gr_init_ctxctl()
1270 gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac, in gf100_gr_init_ctxctl()
1271 &priv->fuc41ad); in gf100_gr_init_ctxctl()
1272 nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); in gf100_gr_init_ctxctl()
1275 nv_wr32(priv, 0x409840, 0xffffffff); in gf100_gr_init_ctxctl()
1276 nv_wr32(priv, 0x41a10c, 0x00000000); in gf100_gr_init_ctxctl()
1277 nv_wr32(priv, 0x40910c, 0x00000000); in gf100_gr_init_ctxctl()
1278 nv_wr32(priv, 0x41a100, 0x00000002); in gf100_gr_init_ctxctl()
1279 nv_wr32(priv, 0x409100, 0x00000002); in gf100_gr_init_ctxctl()
1280 if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001)) in gf100_gr_init_ctxctl()
1281 nv_warn(priv, "0x409800 wait failed\n"); in gf100_gr_init_ctxctl()
1283 nv_wr32(priv, 0x409840, 0xffffffff); in gf100_gr_init_ctxctl()
1284 nv_wr32(priv, 0x409500, 0x7fffffff); in gf100_gr_init_ctxctl()
1285 nv_wr32(priv, 0x409504, 0x00000021); in gf100_gr_init_ctxctl()
1287 nv_wr32(priv, 0x409840, 0xffffffff); in gf100_gr_init_ctxctl()
1288 nv_wr32(priv, 0x409500, 0x00000000); in gf100_gr_init_ctxctl()
1289 nv_wr32(priv, 0x409504, 0x00000010); in gf100_gr_init_ctxctl()
1290 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { in gf100_gr_init_ctxctl()
1291 nv_error(priv, "fuc09 req 0x10 timeout\n"); in gf100_gr_init_ctxctl()
1294 priv->size = nv_rd32(priv, 0x409800); in gf100_gr_init_ctxctl()
1296 nv_wr32(priv, 0x409840, 0xffffffff); in gf100_gr_init_ctxctl()
1297 nv_wr32(priv, 0x409500, 0x00000000); in gf100_gr_init_ctxctl()
1298 nv_wr32(priv, 0x409504, 0x00000016); in gf100_gr_init_ctxctl()
1299 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { in gf100_gr_init_ctxctl()
1300 nv_error(priv, "fuc09 req 0x16 timeout\n"); in gf100_gr_init_ctxctl()
1304 nv_wr32(priv, 0x409840, 0xffffffff); in gf100_gr_init_ctxctl()
1305 nv_wr32(priv, 0x409500, 0x00000000); in gf100_gr_init_ctxctl()
1306 nv_wr32(priv, 0x409504, 0x00000025); in gf100_gr_init_ctxctl()
1307 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { in gf100_gr_init_ctxctl()
1308 nv_error(priv, "fuc09 req 0x25 timeout\n"); in gf100_gr_init_ctxctl()
1312 if (nv_device(priv)->chipset >= 0xe0) { in gf100_gr_init_ctxctl()
1313 nv_wr32(priv, 0x409800, 0x00000000); in gf100_gr_init_ctxctl()
1314 nv_wr32(priv, 0x409500, 0x00000001); in gf100_gr_init_ctxctl()
1315 nv_wr32(priv, 0x409504, 0x00000030); in gf100_gr_init_ctxctl()
1316 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { in gf100_gr_init_ctxctl()
1317 nv_error(priv, "fuc09 req 0x30 timeout\n"); in gf100_gr_init_ctxctl()
1321 nv_wr32(priv, 0x409810, 0xb00095c8); in gf100_gr_init_ctxctl()
1322 nv_wr32(priv, 0x409800, 0x00000000); in gf100_gr_init_ctxctl()
1323 nv_wr32(priv, 0x409500, 0x00000001); in gf100_gr_init_ctxctl()
1324 nv_wr32(priv, 0x409504, 0x00000031); in gf100_gr_init_ctxctl()
1325 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { in gf100_gr_init_ctxctl()
1326 nv_error(priv, "fuc09 req 0x31 timeout\n"); in gf100_gr_init_ctxctl()
1330 nv_wr32(priv, 0x409810, 0x00080420); in gf100_gr_init_ctxctl()
1331 nv_wr32(priv, 0x409800, 0x00000000); in gf100_gr_init_ctxctl()
1332 nv_wr32(priv, 0x409500, 0x00000001); in gf100_gr_init_ctxctl()
1333 nv_wr32(priv, 0x409504, 0x00000032); in gf100_gr_init_ctxctl()
1334 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { in gf100_gr_init_ctxctl()
1335 nv_error(priv, "fuc09 req 0x32 timeout\n"); in gf100_gr_init_ctxctl()
1339 nv_wr32(priv, 0x409614, 0x00000070); in gf100_gr_init_ctxctl()
1340 nv_wr32(priv, 0x409614, 0x00000770); in gf100_gr_init_ctxctl()
1341 nv_wr32(priv, 0x40802c, 0x00000001); in gf100_gr_init_ctxctl()
1344 if (priv->data == NULL) { in gf100_gr_init_ctxctl()
1345 int ret = gf100_grctx_generate(priv); in gf100_gr_init_ctxctl()
1347 nv_error(priv, "failed to construct context\n"); in gf100_gr_init_ctxctl()
1359 nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); in gf100_gr_init_ctxctl()
1360 nv_wr32(priv, 0x4091c0, 0x01000000); in gf100_gr_init_ctxctl()
1362 nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); in gf100_gr_init_ctxctl()
1364 nv_wr32(priv, 0x409180, 0x01000000); in gf100_gr_init_ctxctl()
1367 nv_wr32(priv, 0x409188, i >> 6); in gf100_gr_init_ctxctl()
1368 nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); in gf100_gr_init_ctxctl()
1372 nv_wr32(priv, 0x41a1c0, 0x01000000); in gf100_gr_init_ctxctl()
1374 nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); in gf100_gr_init_ctxctl()
1376 nv_wr32(priv, 0x41a180, 0x01000000); in gf100_gr_init_ctxctl()
1379 nv_wr32(priv, 0x41a188, i >> 6); in gf100_gr_init_ctxctl()
1380 nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); in gf100_gr_init_ctxctl()
1382 nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); in gf100_gr_init_ctxctl()
1385 gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); in gf100_gr_init_ctxctl()
1386 gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000); in gf100_gr_init_ctxctl()
1387 gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800); in gf100_gr_init_ctxctl()
1388 gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00); in gf100_gr_init_ctxctl()
1391 nv_wr32(priv, 0x40910c, 0x00000000); in gf100_gr_init_ctxctl()
1392 nv_wr32(priv, 0x409100, 0x00000002); in gf100_gr_init_ctxctl()
1393 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { in gf100_gr_init_ctxctl()
1394 nv_error(priv, "HUB_INIT timed out\n"); in gf100_gr_init_ctxctl()
1395 gf100_gr_ctxctl_debug(priv); in gf100_gr_init_ctxctl()
1399 priv->size = nv_rd32(priv, 0x409804); in gf100_gr_init_ctxctl()
1400 if (priv->data == NULL) { in gf100_gr_init_ctxctl()
1401 int ret = gf100_grctx_generate(priv); in gf100_gr_init_ctxctl()
1403 nv_error(priv, "failed to construct context\n"); in gf100_gr_init_ctxctl()
1415 struct gf100_gr_priv *priv = (void *)object; in gf100_gr_init() local
1416 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); in gf100_gr_init()
1422 ret = nvkm_gr_init(&priv->base); in gf100_gr_init()
1426 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); in gf100_gr_init()
1427 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); in gf100_gr_init()
1428 nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); in gf100_gr_init()
1429 nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); in gf100_gr_init()
1430 nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); in gf100_gr_init()
1431 nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); in gf100_gr_init()
1432 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); in gf100_gr_init()
1433 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); in gf100_gr_init()
1435 gf100_gr_mmio(priv, oclass->mmio); in gf100_gr_init()
1437 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); in gf100_gr_init()
1438 for (i = 0, gpc = -1; i < priv->tpc_total; i++) { in gf100_gr_init()
1440 gpc = (gpc + 1) % priv->gpc_nr; in gf100_gr_init()
1442 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; in gf100_gr_init()
1447 nv_wr32(priv, GPC_BCAST(0x0980), data[0]); in gf100_gr_init()
1448 nv_wr32(priv, GPC_BCAST(0x0984), data[1]); in gf100_gr_init()
1449 nv_wr32(priv, GPC_BCAST(0x0988), data[2]); in gf100_gr_init()
1450 nv_wr32(priv, GPC_BCAST(0x098c), data[3]); in gf100_gr_init()
1452 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { in gf100_gr_init()
1453 nv_wr32(priv, GPC_UNIT(gpc, 0x0914), in gf100_gr_init()
1454 priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); in gf100_gr_init()
1455 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf100_gr_init()
1456 priv->tpc_total); in gf100_gr_init()
1457 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf100_gr_init()
1460 if (nv_device(priv)->chipset != 0xd7) in gf100_gr_init()
1461 nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918); in gf100_gr_init()
1463 nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); in gf100_gr_init()
1465 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); in gf100_gr_init()
1467 nv_wr32(priv, 0x400500, 0x00010001); in gf100_gr_init()
1469 nv_wr32(priv, 0x400100, 0xffffffff); in gf100_gr_init()
1470 nv_wr32(priv, 0x40013c, 0xffffffff); in gf100_gr_init()
1472 nv_wr32(priv, 0x409c24, 0x000f0000); in gf100_gr_init()
1473 nv_wr32(priv, 0x404000, 0xc0000000); in gf100_gr_init()
1474 nv_wr32(priv, 0x404600, 0xc0000000); in gf100_gr_init()
1475 nv_wr32(priv, 0x408030, 0xc0000000); in gf100_gr_init()
1476 nv_wr32(priv, 0x40601c, 0xc0000000); in gf100_gr_init()
1477 nv_wr32(priv, 0x404490, 0xc0000000); in gf100_gr_init()
1478 nv_wr32(priv, 0x406018, 0xc0000000); in gf100_gr_init()
1479 nv_wr32(priv, 0x405840, 0xc0000000); in gf100_gr_init()
1480 nv_wr32(priv, 0x405844, 0x00ffffff); in gf100_gr_init()
1481 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); in gf100_gr_init()
1482 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); in gf100_gr_init()
1484 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { in gf100_gr_init()
1485 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_init()
1486 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); in gf100_gr_init()
1487 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); in gf100_gr_init()
1488 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); in gf100_gr_init()
1489 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { in gf100_gr_init()
1490 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); in gf100_gr_init()
1491 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); in gf100_gr_init()
1492 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); in gf100_gr_init()
1493 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); in gf100_gr_init()
1494 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); in gf100_gr_init()
1495 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); in gf100_gr_init()
1496 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); in gf100_gr_init()
1498 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); in gf100_gr_init()
1499 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); in gf100_gr_init()
1502 for (rop = 0; rop < priv->rop_nr; rop++) { in gf100_gr_init()
1503 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); in gf100_gr_init()
1504 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); in gf100_gr_init()
1505 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); in gf100_gr_init()
1506 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); in gf100_gr_init()
1509 nv_wr32(priv, 0x400108, 0xffffffff); in gf100_gr_init()
1510 nv_wr32(priv, 0x400138, 0xffffffff); in gf100_gr_init()
1511 nv_wr32(priv, 0x400118, 0xffffffff); in gf100_gr_init()
1512 nv_wr32(priv, 0x400130, 0xffffffff); in gf100_gr_init()
1513 nv_wr32(priv, 0x40011c, 0xffffffff); in gf100_gr_init()
1514 nv_wr32(priv, 0x400134, 0xffffffff); in gf100_gr_init()
1516 nv_wr32(priv, 0x400054, 0x34ce3464); in gf100_gr_init()
1518 gf100_gr_zbc_init(priv); in gf100_gr_init()
1520 return gf100_gr_init_ctxctl(priv); in gf100_gr_init()
1531 gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname, in gf100_gr_ctor_fw() argument
1534 struct nvkm_device *device = nv_device(priv); in gf100_gr_ctor_fw()
1545 nv_error(priv, "failed to load %s\n", fwname); in gf100_gr_ctor_fw()
1559 struct gf100_gr_priv *priv = (void *)object; in gf100_gr_dtor() local
1561 kfree(priv->data); in gf100_gr_dtor()
1563 gf100_gr_dtor_fw(&priv->fuc409c); in gf100_gr_dtor()
1564 gf100_gr_dtor_fw(&priv->fuc409d); in gf100_gr_dtor()
1565 gf100_gr_dtor_fw(&priv->fuc41ac); in gf100_gr_dtor()
1566 gf100_gr_dtor_fw(&priv->fuc41ad); in gf100_gr_dtor()
1568 nvkm_gpuobj_ref(NULL, &priv->unk4188b8); in gf100_gr_dtor()
1569 nvkm_gpuobj_ref(NULL, &priv->unk4188b4); in gf100_gr_dtor()
1571 nvkm_gr_destroy(&priv->base); in gf100_gr_dtor()
1581 struct gf100_gr_priv *priv; in gf100_gr_ctor() local
1589 ret = nvkm_gr_create(parent, engine, bclass, enable, &priv); in gf100_gr_ctor()
1590 *pobject = nv_object(priv); in gf100_gr_ctor()
1594 nv_subdev(priv)->unit = 0x08001000; in gf100_gr_ctor()
1595 nv_subdev(priv)->intr = gf100_gr_intr; in gf100_gr_ctor()
1597 priv->base.units = gf100_gr_units; in gf100_gr_ctor()
1600 nv_info(priv, "using external firmware\n"); in gf100_gr_ctor()
1601 if (gf100_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) || in gf100_gr_ctor()
1602 gf100_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) || in gf100_gr_ctor()
1603 gf100_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || in gf100_gr_ctor()
1604 gf100_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) in gf100_gr_ctor()
1606 priv->firmware = true; in gf100_gr_ctor()
1609 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, in gf100_gr_ctor()
1610 &priv->unk4188b4); in gf100_gr_ctor()
1614 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, in gf100_gr_ctor()
1615 &priv->unk4188b8); in gf100_gr_ctor()
1620 nv_wo32(priv->unk4188b4, i, 0x00000010); in gf100_gr_ctor()
1621 nv_wo32(priv->unk4188b8, i, 0x00000010); in gf100_gr_ctor()
1624 priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; in gf100_gr_ctor()
1625 priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; in gf100_gr_ctor()
1626 for (i = 0; i < priv->gpc_nr; i++) { in gf100_gr_ctor()
1627 priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); in gf100_gr_ctor()
1628 priv->tpc_total += priv->tpc_nr[i]; in gf100_gr_ctor()
1629 priv->ppc_nr[i] = oclass->ppc_nr; in gf100_gr_ctor()
1630 for (j = 0; j < priv->ppc_nr[i]; j++) { in gf100_gr_ctor()
1631 u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4))); in gf100_gr_ctor()
1632 priv->ppc_tpc_nr[i][j] = hweight8(mask); in gf100_gr_ctor()
1637 switch (nv_device(priv)->chipset) { in gf100_gr_ctor()
1639 if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ in gf100_gr_ctor()
1640 priv->magic_not_rop_nr = 0x07; in gf100_gr_ctor()
1642 if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ in gf100_gr_ctor()
1643 priv->magic_not_rop_nr = 0x05; in gf100_gr_ctor()
1645 if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ in gf100_gr_ctor()
1646 priv->magic_not_rop_nr = 0x06; in gf100_gr_ctor()
1650 priv->magic_not_rop_nr = 0x03; in gf100_gr_ctor()
1653 priv->magic_not_rop_nr = 0x01; in gf100_gr_ctor()
1656 priv->magic_not_rop_nr = 0x01; in gf100_gr_ctor()
1659 priv->magic_not_rop_nr = 0x06; in gf100_gr_ctor()
1662 priv->magic_not_rop_nr = 0x03; in gf100_gr_ctor()
1665 priv->magic_not_rop_nr = 0x03; in gf100_gr_ctor()
1669 priv->magic_not_rop_nr = 0x01; in gf100_gr_ctor()
1673 nv_engine(priv)->cclass = *oclass->cclass; in gf100_gr_ctor()
1674 nv_engine(priv)->sclass = oclass->sclass; in gf100_gr_ctor()