415 #define PIPE_SAVE(priv, state, addr)					\  argument
418 		nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr);		\
420 			state[__i] = nv_rd32(priv, NV10_PGRAPH_PIPE_DATA); \
423 #define PIPE_RESTORE(priv, state, addr)					\  argument
426 		nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr);		\
428 			nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \
482 	struct nv10_gr_priv *priv = nv10_gr_priv(chan);  in nv17_gr_mthd_lma_window()  local
494 	nv04_gr_idle(priv);  in nv17_gr_mthd_lma_window()
496 	PIPE_SAVE(priv, pipe_0x0040, 0x0040);  in nv17_gr_mthd_lma_window()
497 	PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200);  in nv17_gr_mthd_lma_window()
499 	PIPE_RESTORE(priv, chan->lma_window, 0x6790);  in nv17_gr_mthd_lma_window()
501 	nv04_gr_idle(priv);  in nv17_gr_mthd_lma_window()
503 	xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);  in nv17_gr_mthd_lma_window()
504 	xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);  in nv17_gr_mthd_lma_window()
506 	PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400);  in nv17_gr_mthd_lma_window()
507 	PIPE_SAVE(priv, pipe_0x64c0, 0x64c0);  in nv17_gr_mthd_lma_window()
508 	PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0);  in nv17_gr_mthd_lma_window()
509 	PIPE_SAVE(priv, pipe_0x6a80, 0x6a80);  in nv17_gr_mthd_lma_window()
511 	nv04_gr_idle(priv);  in nv17_gr_mthd_lma_window()
513 	nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000);  in nv17_gr_mthd_lma_window()
514 	nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000);  in nv17_gr_mthd_lma_window()
515 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);  in nv17_gr_mthd_lma_window()
517 		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);  in nv17_gr_mthd_lma_window()
519 		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv17_gr_mthd_lma_window()
521 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);  in nv17_gr_mthd_lma_window()
523 		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);  in nv17_gr_mthd_lma_window()
525 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);  in nv17_gr_mthd_lma_window()
527 		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv17_gr_mthd_lma_window()
529 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);  in nv17_gr_mthd_lma_window()
530 	nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008);  in nv17_gr_mthd_lma_window()
532 	PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);  in nv17_gr_mthd_lma_window()
534 	nv04_gr_idle(priv);  in nv17_gr_mthd_lma_window()
536 	PIPE_RESTORE(priv, pipe_0x0040, 0x0040);  in nv17_gr_mthd_lma_window()
538 	nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0);  in nv17_gr_mthd_lma_window()
539 	nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1);  in nv17_gr_mthd_lma_window()
541 	PIPE_RESTORE(priv, pipe_0x64c0, 0x64c0);  in nv17_gr_mthd_lma_window()
542 	PIPE_RESTORE(priv, pipe_0x6ab0, 0x6ab0);  in nv17_gr_mthd_lma_window()
543 	PIPE_RESTORE(priv, pipe_0x6a80, 0x6a80);  in nv17_gr_mthd_lma_window()
544 	PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400);  in nv17_gr_mthd_lma_window()
546 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);  in nv17_gr_mthd_lma_window()
547 	nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv17_gr_mthd_lma_window()
549 	nv04_gr_idle(priv);  in nv17_gr_mthd_lma_window()
559 	struct nv10_gr_priv *priv = nv10_gr_priv(chan);  in nv17_gr_mthd_lma_enable()  local
561 	nv04_gr_idle(priv);  in nv17_gr_mthd_lma_enable()
563 	nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100);  in nv17_gr_mthd_lma_enable()
564 	nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000);  in nv17_gr_mthd_lma_enable()
606 nv10_gr_channel(struct nv10_gr_priv *priv)  in nv10_gr_channel()  argument
609 	if (nv_rd32(priv, 0x400144) & 0x00010000) {  in nv10_gr_channel()
610 		int chid = nv_rd32(priv, 0x400148) >> 24;  in nv10_gr_channel()
611 		if (chid < ARRAY_SIZE(priv->chan))  in nv10_gr_channel()
612 			chan = priv->chan[chid];  in nv10_gr_channel()
620 	struct nv10_gr_priv *priv = nv10_gr_priv(chan);  in nv10_gr_save_pipe()  local
623 	PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400);  in nv10_gr_save_pipe()
624 	PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200);  in nv10_gr_save_pipe()
625 	PIPE_SAVE(priv, pipe->pipe_0x6400, 0x6400);  in nv10_gr_save_pipe()
626 	PIPE_SAVE(priv, pipe->pipe_0x6800, 0x6800);  in nv10_gr_save_pipe()
627 	PIPE_SAVE(priv, pipe->pipe_0x6c00, 0x6c00);  in nv10_gr_save_pipe()
628 	PIPE_SAVE(priv, pipe->pipe_0x7000, 0x7000);  in nv10_gr_save_pipe()
629 	PIPE_SAVE(priv, pipe->pipe_0x7400, 0x7400);  in nv10_gr_save_pipe()
630 	PIPE_SAVE(priv, pipe->pipe_0x7800, 0x7800);  in nv10_gr_save_pipe()
631 	PIPE_SAVE(priv, pipe->pipe_0x0040, 0x0040);  in nv10_gr_save_pipe()
632 	PIPE_SAVE(priv, pipe->pipe_0x0000, 0x0000);  in nv10_gr_save_pipe()
638 	struct nv10_gr_priv *priv = nv10_gr_priv(chan);  in nv10_gr_load_pipe()  local
643 	nv04_gr_idle(priv);  in nv10_gr_load_pipe()
645 	xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0);  in nv10_gr_load_pipe()
646 	xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1);  in nv10_gr_load_pipe()
647 	nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000);  in nv10_gr_load_pipe()
648 	nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000);  in nv10_gr_load_pipe()
649 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);  in nv10_gr_load_pipe()
651 		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);  in nv10_gr_load_pipe()
653 		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv10_gr_load_pipe()
655 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);  in nv10_gr_load_pipe()
657 		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000);  in nv10_gr_load_pipe()
659 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);  in nv10_gr_load_pipe()
661 		nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000);  in nv10_gr_load_pipe()
663 	nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);  in nv10_gr_load_pipe()
664 	nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008);  in nv10_gr_load_pipe()
667 	PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200);  in nv10_gr_load_pipe()
668 	nv04_gr_idle(priv);  in nv10_gr_load_pipe()
671 	nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0);  in nv10_gr_load_pipe()
672 	nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1);  in nv10_gr_load_pipe()
673 	PIPE_RESTORE(priv, pipe->pipe_0x6400, 0x6400);  in nv10_gr_load_pipe()
674 	PIPE_RESTORE(priv, pipe->pipe_0x6800, 0x6800);  in nv10_gr_load_pipe()
675 	PIPE_RESTORE(priv, pipe->pipe_0x6c00, 0x6c00);  in nv10_gr_load_pipe()
676 	PIPE_RESTORE(priv, pipe->pipe_0x7000, 0x7000);  in nv10_gr_load_pipe()
677 	PIPE_RESTORE(priv, pipe->pipe_0x7400, 0x7400);  in nv10_gr_load_pipe()
678 	PIPE_RESTORE(priv, pipe->pipe_0x7800, 0x7800);  in nv10_gr_load_pipe()
679 	PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400);  in nv10_gr_load_pipe()
680 	PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000);  in nv10_gr_load_pipe()
681 	PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040);  in nv10_gr_load_pipe()
682 	nv04_gr_idle(priv);  in nv10_gr_load_pipe()
688 	struct nv10_gr_priv *priv = nv10_gr_priv(chan);  in nv10_gr_create_pipe()  local
701 			nv_error(priv, "incomplete pipe init for 0x%x :  %p/%p\n", \  in nv10_gr_create_pipe()
841 nv10_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg)  in nv10_gr_ctx_regs_find_offset()  argument
848 	nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg);  in nv10_gr_ctx_regs_find_offset()
853 nv17_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg)  in nv17_gr_ctx_regs_find_offset()  argument
860 	nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg);  in nv17_gr_ctx_regs_find_offset()
867 	struct nv10_gr_priv *priv = nv10_gr_priv(chan);  in nv10_gr_load_dma_vtxbuf()  local
879 		int class = nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff;  in nv10_gr_load_dma_vtxbuf()
891 	ctx_user = nv_rd32(priv, NV10_PGRAPH_CTX_USER);  in nv10_gr_load_dma_vtxbuf()
893 		ctx_switch[i] = nv_rd32(priv, NV10_PGRAPH_CTX_SWITCH(i));  in nv10_gr_load_dma_vtxbuf()
896 	st2 = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2);  in nv10_gr_load_dma_vtxbuf()
897 	st2_dl = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DL);  in nv10_gr_load_dma_vtxbuf()
898 	st2_dh = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DH);  in nv10_gr_load_dma_vtxbuf()
899 	fifo_ptr = nv_rd32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR);  in nv10_gr_load_dma_vtxbuf()
902 		fifo[i] = nv_rd32(priv, 0x4007a0 + 4 * i);  in nv10_gr_load_dma_vtxbuf()
906 		nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i),  in nv10_gr_load_dma_vtxbuf()
907 			nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(subchan, i)));  in nv10_gr_load_dma_vtxbuf()
908 	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13);  in nv10_gr_load_dma_vtxbuf()
911 	nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0);  in nv10_gr_load_dma_vtxbuf()
912 	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2,  in nv10_gr_load_dma_vtxbuf()
914 	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, inst);  in nv10_gr_load_dma_vtxbuf()
915 	nv_mask(priv, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);  in nv10_gr_load_dma_vtxbuf()
916 	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);  in nv10_gr_load_dma_vtxbuf()
917 	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);  in nv10_gr_load_dma_vtxbuf()
921 		nv_wr32(priv, 0x4007a0 + 4 * i, fifo[i]);  in nv10_gr_load_dma_vtxbuf()
923 	nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr);  in nv10_gr_load_dma_vtxbuf()
924 	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, st2);  in nv10_gr_load_dma_vtxbuf()
925 	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl);  in nv10_gr_load_dma_vtxbuf()
926 	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh);  in nv10_gr_load_dma_vtxbuf()
930 		nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]);  in nv10_gr_load_dma_vtxbuf()
931 	nv_wr32(priv, NV10_PGRAPH_CTX_USER, ctx_user);  in nv10_gr_load_dma_vtxbuf()
937 	struct nv10_gr_priv *priv = nv10_gr_priv(chan);  in nv10_gr_load_context()  local
942 		nv_wr32(priv, nv10_gr_ctx_regs[i], chan->nv10[i]);  in nv10_gr_load_context()
944 	if (nv_device(priv)->card_type >= NV_11 &&  in nv10_gr_load_context()
945 	    nv_device(priv)->chipset >= 0x17) {  in nv10_gr_load_context()
947 			nv_wr32(priv, nv17_gr_ctx_regs[i], chan->nv17[i]);  in nv10_gr_load_context()
952 	inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff;  in nv10_gr_load_context()
955 	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);  in nv10_gr_load_context()
956 	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);  in nv10_gr_load_context()
957 	nv_mask(priv, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000);  in nv10_gr_load_context()
964 	struct nv10_gr_priv *priv = nv10_gr_priv(chan);  in nv10_gr_unload_context()  local
968 		chan->nv10[i] = nv_rd32(priv, nv10_gr_ctx_regs[i]);  in nv10_gr_unload_context()
970 	if (nv_device(priv)->card_type >= NV_11 &&  in nv10_gr_unload_context()
971 	    nv_device(priv)->chipset >= 0x17) {  in nv10_gr_unload_context()
973 			chan->nv17[i] = nv_rd32(priv, nv17_gr_ctx_regs[i]);  in nv10_gr_unload_context()
978 	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000);  in nv10_gr_unload_context()
979 	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);  in nv10_gr_unload_context()
984 nv10_gr_context_switch(struct nv10_gr_priv *priv)  in nv10_gr_context_switch()  argument
991 	spin_lock_irqsave(&priv->lock, flags);  in nv10_gr_context_switch()
992 	nv04_gr_idle(priv);  in nv10_gr_context_switch()
995 	prev = nv10_gr_channel(priv);  in nv10_gr_context_switch()
1000 	chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;  in nv10_gr_context_switch()
1001 	next = priv->chan[chid];  in nv10_gr_context_switch()
1005 	spin_unlock_irqrestore(&priv->lock, flags);  in nv10_gr_context_switch()
1009 	int offset = nv10_gr_ctx_regs_find_offset(priv, reg); \
1015 	int offset = nv17_gr_ctx_regs_find_offset(priv, reg); \
1026 	struct nv10_gr_priv *priv = (void *)engine;  in nv10_gr_context_ctor()  local
1036 	spin_lock_irqsave(&priv->lock, flags);  in nv10_gr_context_ctor()
1037 	if (priv->chan[fifo->chid]) {  in nv10_gr_context_ctor()
1038 		*pobject = nv_object(priv->chan[fifo->chid]);  in nv10_gr_context_ctor()
1040 		spin_unlock_irqrestore(&priv->lock, flags);  in nv10_gr_context_ctor()
1052 	if (nv_device(priv)->card_type >= NV_11 &&  in nv10_gr_context_ctor()
1053 	    nv_device(priv)->chipset >= 0x17) {  in nv10_gr_context_ctor()
1056 					nv_rd32(priv, NV10_PGRAPH_DEBUG_4));  in nv10_gr_context_ctor()
1057 		NV17_WRITE_CTX(0x004006b0, nv_rd32(priv, 0x004006b0));  in nv10_gr_context_ctor()
1067 	priv->chan[fifo->chid] = chan;  in nv10_gr_context_ctor()
1069 	spin_unlock_irqrestore(&priv->lock, flags);  in nv10_gr_context_ctor()
1076 	struct nv10_gr_priv *priv = (void *)object->engine;  in nv10_gr_context_dtor()  local
1080 	spin_lock_irqsave(&priv->lock, flags);  in nv10_gr_context_dtor()
1081 	priv->chan[chan->chid] = NULL;  in nv10_gr_context_dtor()
1082 	spin_unlock_irqrestore(&priv->lock, flags);  in nv10_gr_context_dtor()
1090 	struct nv10_gr_priv *priv = (void *)object->engine;  in nv10_gr_context_fini()  local
1094 	spin_lock_irqsave(&priv->lock, flags);  in nv10_gr_context_fini()
1095 	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);  in nv10_gr_context_fini()
1096 	if (nv10_gr_channel(priv) == chan)  in nv10_gr_context_fini()
1098 	nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);  in nv10_gr_context_fini()
1099 	spin_unlock_irqrestore(&priv->lock, flags);  in nv10_gr_context_fini()
1124 	struct nv10_gr_priv *priv = (void *)engine;  in nv10_gr_tile_prog()  local
1128 	nv04_gr_idle(priv);  in nv10_gr_tile_prog()
1130 	nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit);  in nv10_gr_tile_prog()
1131 	nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch);  in nv10_gr_tile_prog()
1132 	nv_wr32(priv, NV10_PGRAPH_TILE(i), tile->addr);  in nv10_gr_tile_prog()
1154 	struct nv10_gr_priv *priv = (void *)subdev;  in nv10_gr_intr()  local
1158 	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);  in nv10_gr_intr()
1159 	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);  in nv10_gr_intr()
1160 	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);  in nv10_gr_intr()
1161 	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);  in nv10_gr_intr()
1165 	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);  in nv10_gr_intr()
1166 	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;  in nv10_gr_intr()
1170 	spin_lock_irqsave(&priv->lock, flags);  in nv10_gr_intr()
1171 	chan = priv->chan[chid];  in nv10_gr_intr()
1174 	spin_unlock_irqrestore(&priv->lock, flags);  in nv10_gr_intr()
1185 		nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);  in nv10_gr_intr()
1188 		nv10_gr_context_switch(priv);  in nv10_gr_intr()
1191 	nv_wr32(priv, NV03_PGRAPH_INTR, stat);  in nv10_gr_intr()
1192 	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);  in nv10_gr_intr()
1195 		nv_error(priv, "%s", "");  in nv10_gr_intr()
1202 		nv_error(priv,  in nv10_gr_intr()
1216 	struct nv10_gr_priv *priv;  in nv10_gr_ctor()  local
1219 	ret = nvkm_gr_create(parent, engine, oclass, true, &priv);  in nv10_gr_ctor()
1220 	*pobject = nv_object(priv);  in nv10_gr_ctor()
1224 	nv_subdev(priv)->unit = 0x00001000;  in nv10_gr_ctor()
1225 	nv_subdev(priv)->intr = nv10_gr_intr;  in nv10_gr_ctor()
1226 	nv_engine(priv)->cclass = &nv10_gr_cclass;  in nv10_gr_ctor()
1228 	if (nv_device(priv)->chipset <= 0x10)  in nv10_gr_ctor()
1229 		nv_engine(priv)->sclass = nv10_gr_sclass;  in nv10_gr_ctor()
1231 	if (nv_device(priv)->chipset <  0x17 ||  in nv10_gr_ctor()
1232 	    nv_device(priv)->card_type < NV_11)  in nv10_gr_ctor()
1233 		nv_engine(priv)->sclass = nv15_gr_sclass;  in nv10_gr_ctor()
1235 		nv_engine(priv)->sclass = nv17_gr_sclass;  in nv10_gr_ctor()
1237 	nv_engine(priv)->tile_prog = nv10_gr_tile_prog;  in nv10_gr_ctor()
1238 	spin_lock_init(&priv->lock);  in nv10_gr_ctor()
1245 	struct nv10_gr_priv *priv = (void *)object;  in nv10_gr_dtor()  local
1246 	nvkm_gr_destroy(&priv->base);  in nv10_gr_dtor()
1254 	struct nv10_gr_priv *priv = (void *)engine;  in nv10_gr_init()  local
1257 	ret = nvkm_gr_init(&priv->base);  in nv10_gr_init()
1261 	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);  in nv10_gr_init()
1262 	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);  in nv10_gr_init()
1264 	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);  in nv10_gr_init()
1265 	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);  in nv10_gr_init()
1266 	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);  in nv10_gr_init()
1268 	nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);  in nv10_gr_init()
1269 	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31));  in nv10_gr_init()
1271 	if (nv_device(priv)->card_type >= NV_11 &&  in nv10_gr_init()
1272 	    nv_device(priv)->chipset >= 0x17) {  in nv10_gr_init()
1273 		nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x1f000000);  in nv10_gr_init()
1274 		nv_wr32(priv, 0x400a10, 0x03ff3fb6);  in nv10_gr_init()
1275 		nv_wr32(priv, 0x400838, 0x002f8684);  in nv10_gr_init()
1276 		nv_wr32(priv, 0x40083c, 0x00115f3f);  in nv10_gr_init()
1277 		nv_wr32(priv, 0x4006b0, 0x40000020);  in nv10_gr_init()
1279 		nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);  in nv10_gr_init()
1286 	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);  in nv10_gr_init()
1287 	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);  in nv10_gr_init()
1288 	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);  in nv10_gr_init()
1289 	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);  in nv10_gr_init()
1290 	nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);  in nv10_gr_init()
1291 	nv_wr32(priv, NV10_PGRAPH_STATE, 0xFFFFFFFF);  in nv10_gr_init()
1293 	nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);  in nv10_gr_init()
1294 	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);  in nv10_gr_init()
1295 	nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);  in nv10_gr_init()
1302 	struct nv10_gr_priv *priv = (void *)object;  in nv10_gr_fini()  local
1303 	return nvkm_gr_fini(&priv->base, suspend);  in nv10_gr_fini()