Lines Matching refs:priv
105 struct nv20_gr_priv *priv = (void *)object->engine; in nv20_gr_context_init() local
113 nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); in nv20_gr_context_init()
120 struct nv20_gr_priv *priv = (void *)object->engine; in nv20_gr_context_fini() local
124 nv_mask(priv, 0x400720, 0x00000001, 0x00000000); in nv20_gr_context_fini()
125 if (nv_rd32(priv, 0x400144) & 0x00010000) in nv20_gr_context_fini()
126 chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24; in nv20_gr_context_fini()
128 nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4); in nv20_gr_context_fini()
129 nv_wr32(priv, 0x400788, 0x00000002); in nv20_gr_context_fini()
130 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); in nv20_gr_context_fini()
131 nv_wr32(priv, 0x400144, 0x10000000); in nv20_gr_context_fini()
132 nv_mask(priv, 0x400148, 0xff000000, 0x1f000000); in nv20_gr_context_fini()
134 nv_mask(priv, 0x400720, 0x00000001, 0x00000001); in nv20_gr_context_fini()
136 nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000); in nv20_gr_context_fini()
162 struct nv20_gr_priv *priv = (void *)engine; in nv20_gr_tile_prog() local
166 nv04_gr_idle(priv); in nv20_gr_tile_prog()
168 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_gr_tile_prog()
169 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_gr_tile_prog()
170 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); in nv20_gr_tile_prog()
172 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); in nv20_gr_tile_prog()
173 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_gr_tile_prog()
174 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); in nv20_gr_tile_prog()
175 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_gr_tile_prog()
176 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); in nv20_gr_tile_prog()
177 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr); in nv20_gr_tile_prog()
180 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv20_gr_tile_prog()
181 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); in nv20_gr_tile_prog()
182 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp); in nv20_gr_tile_prog()
194 struct nv20_gr_priv *priv = (void *)subdev; in nv20_gr_intr() local
195 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); in nv20_gr_intr()
196 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); in nv20_gr_intr()
197 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); in nv20_gr_intr()
198 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); in nv20_gr_intr()
202 u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); in nv20_gr_intr()
203 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; in nv20_gr_intr()
216 nv_wr32(priv, NV03_PGRAPH_INTR, stat); in nv20_gr_intr()
217 nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); in nv20_gr_intr()
220 nv_error(priv, "%s", ""); in nv20_gr_intr()
227 nv_error(priv, in nv20_gr_intr()
241 struct nv20_gr_priv *priv; in nv20_gr_ctor() local
244 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); in nv20_gr_ctor()
245 *pobject = nv_object(priv); in nv20_gr_ctor()
249 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, in nv20_gr_ctor()
250 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); in nv20_gr_ctor()
254 nv_subdev(priv)->unit = 0x00001000; in nv20_gr_ctor()
255 nv_subdev(priv)->intr = nv20_gr_intr; in nv20_gr_ctor()
256 nv_engine(priv)->cclass = &nv20_gr_cclass; in nv20_gr_ctor()
257 nv_engine(priv)->sclass = nv20_gr_sclass; in nv20_gr_ctor()
258 nv_engine(priv)->tile_prog = nv20_gr_tile_prog; in nv20_gr_ctor()
265 struct nv20_gr_priv *priv = (void *)object; in nv20_gr_dtor() local
266 nvkm_gpuobj_ref(NULL, &priv->ctxtab); in nv20_gr_dtor()
267 nvkm_gr_destroy(&priv->base); in nv20_gr_dtor()
274 struct nv20_gr_priv *priv = (void *)engine; in nv20_gr_init() local
279 ret = nvkm_gr_init(&priv->base); in nv20_gr_init()
283 nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); in nv20_gr_init()
285 if (nv_device(priv)->chipset == 0x20) { in nv20_gr_init()
286 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000); in nv20_gr_init()
288 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); in nv20_gr_init()
289 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); in nv20_gr_init()
291 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000); in nv20_gr_init()
293 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); in nv20_gr_init()
294 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); in nv20_gr_init()
297 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv20_gr_init()
298 nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv20_gr_init()
300 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv20_gr_init()
301 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv20_gr_init()
302 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); in nv20_gr_init()
303 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ in nv20_gr_init()
304 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); in nv20_gr_init()
305 nv_wr32(priv, 0x40009C , 0x00000040); in nv20_gr_init()
307 if (nv_device(priv)->chipset >= 0x25) { in nv20_gr_init()
308 nv_wr32(priv, 0x400890, 0x00a8cfff); in nv20_gr_init()
309 nv_wr32(priv, 0x400610, 0x304B1FB6); in nv20_gr_init()
310 nv_wr32(priv, 0x400B80, 0x1cbd3883); in nv20_gr_init()
311 nv_wr32(priv, 0x400B84, 0x44000000); in nv20_gr_init()
312 nv_wr32(priv, 0x400098, 0x40000080); in nv20_gr_init()
313 nv_wr32(priv, 0x400B88, 0x000000ff); in nv20_gr_init()
316 nv_wr32(priv, 0x400880, 0x0008c7df); in nv20_gr_init()
317 nv_wr32(priv, 0x400094, 0x00000005); in nv20_gr_init()
318 nv_wr32(priv, 0x400B80, 0x45eae20e); in nv20_gr_init()
319 nv_wr32(priv, 0x400B84, 0x24000000); in nv20_gr_init()
320 nv_wr32(priv, 0x400098, 0x00000040); in nv20_gr_init()
321 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038); in nv20_gr_init()
322 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); in nv20_gr_init()
323 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038); in nv20_gr_init()
324 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); in nv20_gr_init()
331 nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324)); in nv20_gr_init()
332 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); in nv20_gr_init()
333 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324)); in nv20_gr_init()
335 nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); in nv20_gr_init()
336 nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); in nv20_gr_init()
338 tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00; in nv20_gr_init()
339 nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); in nv20_gr_init()
340 tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100; in nv20_gr_init()
341 nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); in nv20_gr_init()
344 vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; in nv20_gr_init()
345 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); in nv20_gr_init()
346 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); in nv20_gr_init()
347 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); in nv20_gr_init()
348 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200)); in nv20_gr_init()
349 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); in nv20_gr_init()
350 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204)); in nv20_gr_init()
351 nv_wr32(priv, 0x400820, 0); in nv20_gr_init()
352 nv_wr32(priv, 0x400824, 0); in nv20_gr_init()
353 nv_wr32(priv, 0x400864, vramsz - 1); in nv20_gr_init()
354 nv_wr32(priv, 0x400868, vramsz - 1); in nv20_gr_init()
357 nv_wr32(priv, 0x400B20, 0x00000000); in nv20_gr_init()
358 nv_wr32(priv, 0x400B04, 0xFFFFFFFF); in nv20_gr_init()
360 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); in nv20_gr_init()
361 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); in nv20_gr_init()
362 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); in nv20_gr_init()
363 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); in nv20_gr_init()