131 	struct nv20_gr_priv *priv;  in nv30_gr_ctor()  local
134 	ret = nvkm_gr_create(parent, engine, oclass, true, &priv);  in nv30_gr_ctor()
135 	*pobject = nv_object(priv);  in nv30_gr_ctor()
139 	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,  in nv30_gr_ctor()
140 			      NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);  in nv30_gr_ctor()
144 	nv_subdev(priv)->unit = 0x00001000;  in nv30_gr_ctor()
145 	nv_subdev(priv)->intr = nv20_gr_intr;  in nv30_gr_ctor()
146 	nv_engine(priv)->cclass = &nv30_gr_cclass;  in nv30_gr_ctor()
147 	nv_engine(priv)->sclass = nv30_gr_sclass;  in nv30_gr_ctor()
148 	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;  in nv30_gr_ctor()
156 	struct nv20_gr_priv *priv = (void *)engine;  in nv30_gr_init()  local
160 	ret = nvkm_gr_init(&priv->base);  in nv30_gr_init()
164 	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);  in nv30_gr_init()
166 	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);  in nv30_gr_init()
167 	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);  in nv30_gr_init()
169 	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);  in nv30_gr_init()
170 	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);  in nv30_gr_init()
171 	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);  in nv30_gr_init()
172 	nv_wr32(priv, 0x400890, 0x01b463ff);  in nv30_gr_init()
173 	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475);  in nv30_gr_init()
174 	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);  in nv30_gr_init()
175 	nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);  in nv30_gr_init()
176 	nv_wr32(priv, 0x400B80, 0x1003d888);  in nv30_gr_init()
177 	nv_wr32(priv, 0x400B84, 0x0c000000);  in nv30_gr_init()
178 	nv_wr32(priv, 0x400098, 0x00000000);  in nv30_gr_init()
179 	nv_wr32(priv, 0x40009C, 0x0005ad00);  in nv30_gr_init()
180 	nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */  in nv30_gr_init()
181 	nv_wr32(priv, 0x4000a0, 0x00000000);  in nv30_gr_init()
182 	nv_wr32(priv, 0x4000a4, 0x00000008);  in nv30_gr_init()
183 	nv_wr32(priv, 0x4008a8, 0xb784a400);  in nv30_gr_init()
184 	nv_wr32(priv, 0x400ba0, 0x002f8685);  in nv30_gr_init()
185 	nv_wr32(priv, 0x400ba4, 0x00231f3f);  in nv30_gr_init()
186 	nv_wr32(priv, 0x4008a4, 0x40000020);  in nv30_gr_init()
188 	if (nv_device(priv)->chipset == 0x34) {  in nv30_gr_init()
189 		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);  in nv30_gr_init()
190 		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201);  in nv30_gr_init()
191 		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);  in nv30_gr_init()
192 		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008);  in nv30_gr_init()
193 		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);  in nv30_gr_init()
194 		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032);  in nv30_gr_init()
195 		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004);  in nv30_gr_init()
196 		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002);  in nv30_gr_init()
199 	nv_wr32(priv, 0x4000c0, 0x00000016);  in nv30_gr_init()
205 	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);  in nv30_gr_init()
206 	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);  in nv30_gr_init()
207 	nv_wr32(priv, 0x0040075c             , 0x00000001);  in nv30_gr_init()
211 	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));  in nv30_gr_init()
212 	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));  in nv30_gr_init()
213 	if (nv_device(priv)->chipset != 0x34) {  in nv30_gr_init()
214 		nv_wr32(priv, 0x400750, 0x00EA0000);  in nv30_gr_init()
215 		nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200));  in nv30_gr_init()
216 		nv_wr32(priv, 0x400750, 0x00EA0004);  in nv30_gr_init()
217 		nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204));  in nv30_gr_init()