Lines Matching refs:priv
45 struct nv40_gr_priv *priv = (void *)gr; in nv40_gr_units() local
47 return nv_rd32(priv, 0x1540); in nv40_gr_units()
140 struct nv40_gr_priv *priv = (void *)engine; in nv40_gr_context_ctor() local
144 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, in nv40_gr_context_ctor()
150 nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan)); in nv40_gr_context_ctor()
158 struct nv40_gr_priv *priv = (void *)object->engine; in nv40_gr_context_fini() local
163 nv_mask(priv, 0x400720, 0x00000001, 0x00000000); in nv40_gr_context_fini()
165 if (nv_rd32(priv, 0x40032c) == inst) { in nv40_gr_context_fini()
167 nv_wr32(priv, 0x400720, 0x00000000); in nv40_gr_context_fini()
168 nv_wr32(priv, 0x400784, inst); in nv40_gr_context_fini()
169 nv_mask(priv, 0x400310, 0x00000020, 0x00000020); in nv40_gr_context_fini()
170 nv_mask(priv, 0x400304, 0x00000001, 0x00000001); in nv40_gr_context_fini()
171 if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) { in nv40_gr_context_fini()
172 u32 insn = nv_rd32(priv, 0x400308); in nv40_gr_context_fini()
173 nv_warn(priv, "ctxprog timeout 0x%08x\n", insn); in nv40_gr_context_fini()
178 nv_mask(priv, 0x40032c, 0x01000000, 0x00000000); in nv40_gr_context_fini()
181 if (nv_rd32(priv, 0x400330) == inst) in nv40_gr_context_fini()
182 nv_mask(priv, 0x400330, 0x01000000, 0x00000000); in nv40_gr_context_fini()
184 nv_mask(priv, 0x400720, 0x00000001, 0x00000001); in nv40_gr_context_fini()
210 struct nv40_gr_priv *priv = (void *)engine; in nv40_gr_tile_prog() local
214 nv04_gr_idle(priv); in nv40_gr_tile_prog()
216 switch (nv_device(priv)->chipset) { in nv40_gr_tile_prog()
223 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile_prog()
224 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile_prog()
225 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile_prog()
226 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile_prog()
227 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile_prog()
228 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile_prog()
229 switch (nv_device(priv)->chipset) { in nv40_gr_tile_prog()
232 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile_prog()
233 nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile_prog()
238 nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile_prog()
239 nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile_prog()
247 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile_prog()
248 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile_prog()
249 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile_prog()
259 nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile_prog()
260 nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile_prog()
261 nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile_prog()
262 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile_prog()
263 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile_prog()
264 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile_prog()
265 switch (nv_device(priv)->chipset) { in nv40_gr_tile_prog()
269 nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile_prog()
270 nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile_prog()
290 struct nv40_gr_priv *priv = (void *)subdev; in nv40_gr_intr() local
291 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); in nv40_gr_intr()
292 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); in nv40_gr_intr()
293 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); in nv40_gr_intr()
294 u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff; in nv40_gr_intr()
295 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); in nv40_gr_intr()
298 u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); in nv40_gr_intr()
299 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff; in nv40_gr_intr()
315 nv_mask(priv, 0x402000, 0, 0); in nv40_gr_intr()
319 nv_wr32(priv, NV03_PGRAPH_INTR, stat); in nv40_gr_intr()
320 nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); in nv40_gr_intr()
323 nv_error(priv, "%s", ""); in nv40_gr_intr()
330 nv_error(priv, in nv40_gr_intr()
344 struct nv40_gr_priv *priv; in nv40_gr_ctor() local
347 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); in nv40_gr_ctor()
348 *pobject = nv_object(priv); in nv40_gr_ctor()
352 nv_subdev(priv)->unit = 0x00001000; in nv40_gr_ctor()
353 nv_subdev(priv)->intr = nv40_gr_intr; in nv40_gr_ctor()
354 nv_engine(priv)->cclass = &nv40_gr_cclass; in nv40_gr_ctor()
355 if (nv44_gr_class(priv)) in nv40_gr_ctor()
356 nv_engine(priv)->sclass = nv44_gr_sclass; in nv40_gr_ctor()
358 nv_engine(priv)->sclass = nv40_gr_sclass; in nv40_gr_ctor()
359 nv_engine(priv)->tile_prog = nv40_gr_tile_prog; in nv40_gr_ctor()
361 priv->base.units = nv40_gr_units; in nv40_gr_ctor()
370 struct nv40_gr_priv *priv = (void *)engine; in nv40_gr_init() local
374 ret = nvkm_gr_init(&priv->base); in nv40_gr_init()
379 ret = nv40_grctx_init(nv_device(priv), &priv->size); in nv40_gr_init()
384 nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); in nv40_gr_init()
386 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv40_gr_init()
387 nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv40_gr_init()
389 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv40_gr_init()
390 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv40_gr_init()
391 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); in nv40_gr_init()
392 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055); in nv40_gr_init()
393 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); in nv40_gr_init()
394 nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); in nv40_gr_init()
396 nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); in nv40_gr_init()
397 nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); in nv40_gr_init()
399 j = nv_rd32(priv, 0x1540) & 0xff; in nv40_gr_init()
403 nv_wr32(priv, 0x405000, i); in nv40_gr_init()
406 if (nv_device(priv)->chipset == 0x40) { in nv40_gr_init()
407 nv_wr32(priv, 0x4009b0, 0x83280fff); in nv40_gr_init()
408 nv_wr32(priv, 0x4009b4, 0x000000a0); in nv40_gr_init()
410 nv_wr32(priv, 0x400820, 0x83280eff); in nv40_gr_init()
411 nv_wr32(priv, 0x400824, 0x000000a0); in nv40_gr_init()
414 switch (nv_device(priv)->chipset) { in nv40_gr_init()
417 nv_wr32(priv, 0x4009b8, 0x0078e366); in nv40_gr_init()
418 nv_wr32(priv, 0x4009bc, 0x0000014c); in nv40_gr_init()
423 nv_wr32(priv, 0x400828, 0x007596ff); in nv40_gr_init()
424 nv_wr32(priv, 0x40082c, 0x00000108); in nv40_gr_init()
427 nv_wr32(priv, 0x400828, 0x0072cb77); in nv40_gr_init()
428 nv_wr32(priv, 0x40082c, 0x00000108); in nv40_gr_init()
435 nv_wr32(priv, 0x400860, 0); in nv40_gr_init()
436 nv_wr32(priv, 0x400864, 0); in nv40_gr_init()
441 nv_wr32(priv, 0x400828, 0x07830610); in nv40_gr_init()
442 nv_wr32(priv, 0x40082c, 0x0000016A); in nv40_gr_init()
448 nv_wr32(priv, 0x400b38, 0x2ffff800); in nv40_gr_init()
449 nv_wr32(priv, 0x400b3c, 0x00006000); in nv40_gr_init()
452 switch (nv_device(priv)->chipset) { in nv40_gr_init()
455 nv_wr32(priv, 0x400bc4, 0x1003d888); in nv40_gr_init()
456 nv_wr32(priv, 0x400bbc, 0xb7a7b500); in nv40_gr_init()
459 nv_wr32(priv, 0x400bc4, 0x0000e024); in nv40_gr_init()
460 nv_wr32(priv, 0x400bbc, 0xb7a7b520); in nv40_gr_init()
465 nv_wr32(priv, 0x400bc4, 0x1003d888); in nv40_gr_init()
466 nv_wr32(priv, 0x400bbc, 0xb7a7b540); in nv40_gr_init()
477 vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; in nv40_gr_init()
478 switch (nv_device(priv)->chipset) { in nv40_gr_init()
480 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); in nv40_gr_init()
481 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); in nv40_gr_init()
482 nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200)); in nv40_gr_init()
483 nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204)); in nv40_gr_init()
484 nv_wr32(priv, 0x400820, 0); in nv40_gr_init()
485 nv_wr32(priv, 0x400824, 0); in nv40_gr_init()
486 nv_wr32(priv, 0x400864, vramsz); in nv40_gr_init()
487 nv_wr32(priv, 0x400868, vramsz); in nv40_gr_init()
490 switch (nv_device(priv)->chipset) { in nv40_gr_init()
498 nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200)); in nv40_gr_init()
499 nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204)); in nv40_gr_init()
502 nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200)); in nv40_gr_init()
503 nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204)); in nv40_gr_init()
506 nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200)); in nv40_gr_init()
507 nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204)); in nv40_gr_init()
508 nv_wr32(priv, 0x400840, 0); in nv40_gr_init()
509 nv_wr32(priv, 0x400844, 0); in nv40_gr_init()
510 nv_wr32(priv, 0x4008A0, vramsz); in nv40_gr_init()
511 nv_wr32(priv, 0x4008A4, vramsz); in nv40_gr_init()