Lines Matching refs:priv
45 struct nv50_gr_priv *priv = (void *)gr; in nv50_gr_units() local
47 return nv_rd32(priv, 0x1540); in nv50_gr_units()
146 struct nv50_gr_priv *priv = (void *)engine; in nv50_gr_context_ctor() local
150 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, in nv50_gr_context_ctor()
156 nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan)); in nv50_gr_context_ctor()
221 nvkm_pgr_vstatus_print(struct nv50_gr_priv *priv, int r, in nvkm_pgr_vstatus_print() argument
226 nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status); in nvkm_pgr_vstatus_print()
242 struct nv50_gr_priv *priv = (void *)engine; in g84_gr_tlb_flush() local
248 spin_lock_irqsave(&priv->lock, flags); in g84_gr_tlb_flush()
249 nv_mask(priv, 0x400500, 0x00000001, 0x00000000); in g84_gr_tlb_flush()
255 for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
260 for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
265 for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
273 nv_error(priv, "PGRAPH TLB flush idle timeout fail\n"); in g84_gr_tlb_flush()
275 tmp = nv_rd32(priv, 0x400700); in g84_gr_tlb_flush()
276 nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp); in g84_gr_tlb_flush()
280 nvkm_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0, in g84_gr_tlb_flush()
281 nv_rd32(priv, 0x400380)); in g84_gr_tlb_flush()
282 nvkm_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1, in g84_gr_tlb_flush()
283 nv_rd32(priv, 0x400384)); in g84_gr_tlb_flush()
284 nvkm_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2, in g84_gr_tlb_flush()
285 nv_rd32(priv, 0x400388)); in g84_gr_tlb_flush()
289 nv_wr32(priv, 0x100c80, 0x00000001); in g84_gr_tlb_flush()
290 if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) in g84_gr_tlb_flush()
291 nv_error(priv, "vm flush timeout\n"); in g84_gr_tlb_flush()
292 nv_mask(priv, 0x400500, 0x00000001, 0x00000001); in g84_gr_tlb_flush()
293 spin_unlock_irqrestore(&priv->lock, flags); in g84_gr_tlb_flush()
430 nv50_priv_prop_trap(struct nv50_gr_priv *priv, in nv50_priv_prop_trap() argument
433 u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); in nv50_priv_prop_trap()
434 u32 e10 = nv_rd32(priv, ustatus_addr + 0x08); in nv50_priv_prop_trap()
435 u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c); in nv50_priv_prop_trap()
436 u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); in nv50_priv_prop_trap()
437 u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); in nv50_priv_prop_trap()
438 u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); in nv50_priv_prop_trap()
439 u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); in nv50_priv_prop_trap()
445 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", in nv50_priv_prop_trap()
450 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", in nv50_priv_prop_trap()
454 nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", in nv50_priv_prop_trap()
460 nv_error(priv, "TRAP_PROP - TP %d -", tp); in nv50_priv_prop_trap()
464 nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", in nv50_priv_prop_trap()
469 nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display) in nv50_priv_mp_trap() argument
471 u32 units = nv_rd32(priv, 0x1540); in nv50_priv_mp_trap()
478 if (nv_device(priv)->chipset < 0xa0) in nv50_priv_mp_trap()
482 mp10 = nv_rd32(priv, addr + 0x10); in nv50_priv_mp_trap()
483 status = nv_rd32(priv, addr + 0x14); in nv50_priv_mp_trap()
487 nv_rd32(priv, addr + 0x20); in nv50_priv_mp_trap()
488 pc = nv_rd32(priv, addr + 0x24); in nv50_priv_mp_trap()
489 oplow = nv_rd32(priv, addr + 0x70); in nv50_priv_mp_trap()
490 ophigh = nv_rd32(priv, addr + 0x74); in nv50_priv_mp_trap()
491 nv_error(priv, "TRAP_MP_EXEC - " in nv50_priv_mp_trap()
498 nv_wr32(priv, addr + 0x10, mp10); in nv50_priv_mp_trap()
499 nv_wr32(priv, addr + 0x14, 0); in nv50_priv_mp_trap()
503 nv_error(priv, "TRAP_MP_EXEC - TP %d: " in nv50_priv_mp_trap()
508 nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old, in nv50_priv_tp_trap() argument
512 u32 units = nv_rd32(priv, 0x1540); in nv50_priv_tp_trap()
518 if (nv_device(priv)->chipset < 0xa0) in nv50_priv_tp_trap()
522 ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff; in nv50_priv_tp_trap()
529 nv_error(priv, "magic set %d:\n", i); in nv50_priv_tp_trap()
531 nv_error(priv, "\t0x%08x: 0x%08x\n", r, in nv50_priv_tp_trap()
532 nv_rd32(priv, r)); in nv50_priv_tp_trap()
534 nv_error(priv, "%s - TP%d:", name, i); in nv50_priv_tp_trap()
544 nv50_priv_mp_trap(priv, i, display); in nv50_priv_tp_trap()
548 nv_error(priv, "%s - TP%d:", name, i); in nv50_priv_tp_trap()
557 priv, ustatus_addr, ustatus, i); in nv50_priv_tp_trap()
563 nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); in nv50_priv_tp_trap()
565 nv_wr32(priv, ustatus_addr, 0xc0000000); in nv50_priv_tp_trap()
569 nv_warn(priv, "%s - No TPs claiming errors?\n", name); in nv50_priv_tp_trap()
573 nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display, in nv50_gr_trap_handler() argument
576 u32 status = nv_rd32(priv, 0x400108); in nv50_gr_trap_handler()
580 nv_error(priv, "TRAP: no units reporting traps?\n"); in nv50_gr_trap_handler()
588 ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff; in nv50_gr_trap_handler()
590 nv_error(priv, "TRAP_DISPATCH - no ustatus?\n"); in nv50_gr_trap_handler()
593 nv_wr32(priv, 0x400500, 0x00000000); in nv50_gr_trap_handler()
597 u32 addr = nv_rd32(priv, 0x400808); in nv50_gr_trap_handler()
600 u32 datal = nv_rd32(priv, 0x40080c); in nv50_gr_trap_handler()
601 u32 datah = nv_rd32(priv, 0x400810); in nv50_gr_trap_handler()
602 u32 class = nv_rd32(priv, 0x400814); in nv50_gr_trap_handler()
603 u32 r848 = nv_rd32(priv, 0x400848); in nv50_gr_trap_handler()
605 nv_error(priv, "TRAP DISPATCH_FAULT\n"); in nv50_gr_trap_handler()
607 nv_error(priv, in nv50_gr_trap_handler()
614 nv_error(priv, "no stuck command?\n"); in nv50_gr_trap_handler()
617 nv_wr32(priv, 0x400808, 0); in nv50_gr_trap_handler()
618 nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3); in nv50_gr_trap_handler()
619 nv_wr32(priv, 0x400848, 0); in nv50_gr_trap_handler()
624 u32 addr = nv_rd32(priv, 0x40084c); in nv50_gr_trap_handler()
627 u32 data = nv_rd32(priv, 0x40085c); in nv50_gr_trap_handler()
628 u32 class = nv_rd32(priv, 0x400814); in nv50_gr_trap_handler()
630 nv_error(priv, "TRAP DISPATCH_QUERY\n"); in nv50_gr_trap_handler()
632 nv_error(priv, in nv50_gr_trap_handler()
639 nv_error(priv, "no stuck command?\n"); in nv50_gr_trap_handler()
642 nv_wr32(priv, 0x40084c, 0); in nv50_gr_trap_handler()
647 nv_error(priv, "TRAP_DISPATCH (unknown " in nv50_gr_trap_handler()
651 nv_wr32(priv, 0x400804, 0xc0000000); in nv50_gr_trap_handler()
652 nv_wr32(priv, 0x400108, 0x001); in nv50_gr_trap_handler()
660 u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff; in nv50_gr_trap_handler()
662 nv_error(priv, "TRAP_M2MF"); in nv50_gr_trap_handler()
665 nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n", in nv50_gr_trap_handler()
666 nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808), in nv50_gr_trap_handler()
667 nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810)); in nv50_gr_trap_handler()
672 nv_wr32(priv, 0x400040, 2); in nv50_gr_trap_handler()
673 nv_wr32(priv, 0x400040, 0); in nv50_gr_trap_handler()
674 nv_wr32(priv, 0x406800, 0xc0000000); in nv50_gr_trap_handler()
675 nv_wr32(priv, 0x400108, 0x002); in nv50_gr_trap_handler()
681 u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff; in nv50_gr_trap_handler()
683 nv_error(priv, "TRAP_VFETCH"); in nv50_gr_trap_handler()
686 nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n", in nv50_gr_trap_handler()
687 nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08), in nv50_gr_trap_handler()
688 nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10)); in nv50_gr_trap_handler()
691 nv_wr32(priv, 0x400c04, 0xc0000000); in nv50_gr_trap_handler()
692 nv_wr32(priv, 0x400108, 0x004); in nv50_gr_trap_handler()
698 ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff; in nv50_gr_trap_handler()
700 nv_error(priv, "TRAP_STRMOUT"); in nv50_gr_trap_handler()
703 nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n", in nv50_gr_trap_handler()
704 nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808), in nv50_gr_trap_handler()
705 nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810)); in nv50_gr_trap_handler()
710 nv_wr32(priv, 0x400040, 0x80); in nv50_gr_trap_handler()
711 nv_wr32(priv, 0x400040, 0); in nv50_gr_trap_handler()
712 nv_wr32(priv, 0x401800, 0xc0000000); in nv50_gr_trap_handler()
713 nv_wr32(priv, 0x400108, 0x008); in nv50_gr_trap_handler()
719 ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff; in nv50_gr_trap_handler()
721 nv_error(priv, "TRAP_CCACHE"); in nv50_gr_trap_handler()
724 nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x" in nv50_gr_trap_handler()
726 nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004), in nv50_gr_trap_handler()
727 nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c), in nv50_gr_trap_handler()
728 nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014), in nv50_gr_trap_handler()
729 nv_rd32(priv, 0x40501c)); in nv50_gr_trap_handler()
733 nv_wr32(priv, 0x405018, 0xc0000000); in nv50_gr_trap_handler()
734 nv_wr32(priv, 0x400108, 0x010); in nv50_gr_trap_handler()
742 ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff; in nv50_gr_trap_handler()
744 nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus); in nv50_gr_trap_handler()
745 nv_wr32(priv, 0x402000, 0xc0000000); in nv50_gr_trap_handler()
751 nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display, in nv50_gr_trap_handler()
753 nv_wr32(priv, 0x400108, 0x040); in nv50_gr_trap_handler()
759 nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display, in nv50_gr_trap_handler()
761 nv_wr32(priv, 0x400108, 0x080); in nv50_gr_trap_handler()
768 nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, in nv50_gr_trap_handler()
770 nv_wr32(priv, 0x400108, 0x100); in nv50_gr_trap_handler()
776 nv_error(priv, "TRAP: unknown 0x%08x\n", status); in nv50_gr_trap_handler()
777 nv_wr32(priv, 0x400108, status); in nv50_gr_trap_handler()
790 struct nv50_gr_priv *priv = (void *)subdev; in nv50_gr_intr() local
791 u32 stat = nv_rd32(priv, 0x400100); in nv50_gr_intr()
792 u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff; in nv50_gr_intr()
793 u32 addr = nv_rd32(priv, 0x400704); in nv50_gr_intr()
796 u32 data = nv_rd32(priv, 0x400708); in nv50_gr_intr()
797 u32 class = nv_rd32(priv, 0x400814); in nv50_gr_intr()
812 u32 ecode = nv_rd32(priv, 0x400110); in nv50_gr_intr()
813 nv_error(priv, "DATA_ERROR "); in nv50_gr_intr()
820 if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12, in nv50_gr_intr()
826 nv_wr32(priv, 0x400100, stat); in nv50_gr_intr()
827 nv_wr32(priv, 0x400500, 0x00010001); in nv50_gr_intr()
832 nv_error(priv, "%s", ""); in nv50_gr_intr()
836 nv_error(priv, in nv50_gr_intr()
842 if (nv_rd32(priv, 0x400824) & (1 << 31)) in nv50_gr_intr()
843 nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31)); in nv50_gr_intr()
853 struct nv50_gr_priv *priv; in nv50_gr_ctor() local
856 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); in nv50_gr_ctor()
857 *pobject = nv_object(priv); in nv50_gr_ctor()
861 nv_subdev(priv)->unit = 0x00201000; in nv50_gr_ctor()
862 nv_subdev(priv)->intr = nv50_gr_intr; in nv50_gr_ctor()
863 nv_engine(priv)->cclass = &nv50_gr_cclass; in nv50_gr_ctor()
865 priv->base.units = nv50_gr_units; in nv50_gr_ctor()
867 switch (nv_device(priv)->chipset) { in nv50_gr_ctor()
869 nv_engine(priv)->sclass = nv50_gr_sclass; in nv50_gr_ctor()
877 nv_engine(priv)->sclass = g84_gr_sclass; in nv50_gr_ctor()
882 nv_engine(priv)->sclass = gt200_gr_sclass; in nv50_gr_ctor()
887 nv_engine(priv)->sclass = gt215_gr_sclass; in nv50_gr_ctor()
890 nv_engine(priv)->sclass = mcp89_gr_sclass; in nv50_gr_ctor()
896 if (nv_device(priv)->chipset != 0x50 && in nv50_gr_ctor()
897 nv_device(priv)->chipset != 0xac) in nv50_gr_ctor()
898 nv_engine(priv)->tlb_flush = g84_gr_tlb_flush; in nv50_gr_ctor()
900 spin_lock_init(&priv->lock); in nv50_gr_ctor()
907 struct nv50_gr_priv *priv = (void *)object; in nv50_gr_init() local
910 ret = nvkm_gr_init(&priv->base); in nv50_gr_init()
915 nv_wr32(priv, 0x40008c, 0x00000004); in nv50_gr_init()
918 nv_wr32(priv, 0x400804, 0xc0000000); in nv50_gr_init()
919 nv_wr32(priv, 0x406800, 0xc0000000); in nv50_gr_init()
920 nv_wr32(priv, 0x400c04, 0xc0000000); in nv50_gr_init()
921 nv_wr32(priv, 0x401800, 0xc0000000); in nv50_gr_init()
922 nv_wr32(priv, 0x405018, 0xc0000000); in nv50_gr_init()
923 nv_wr32(priv, 0x402000, 0xc0000000); in nv50_gr_init()
925 units = nv_rd32(priv, 0x001540); in nv50_gr_init()
930 if (nv_device(priv)->chipset < 0xa0) { in nv50_gr_init()
931 nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000); in nv50_gr_init()
932 nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000); in nv50_gr_init()
933 nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000); in nv50_gr_init()
935 nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000); in nv50_gr_init()
936 nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000); in nv50_gr_init()
937 nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000); in nv50_gr_init()
941 nv_wr32(priv, 0x400108, 0xffffffff); in nv50_gr_init()
942 nv_wr32(priv, 0x400138, 0xffffffff); in nv50_gr_init()
943 nv_wr32(priv, 0x400100, 0xffffffff); in nv50_gr_init()
944 nv_wr32(priv, 0x40013c, 0xffffffff); in nv50_gr_init()
945 nv_wr32(priv, 0x400500, 0x00010001); in nv50_gr_init()
948 ret = nv50_grctx_init(nv_device(priv), &priv->size); in nv50_gr_init()
952 nv_wr32(priv, 0x400824, 0x00000000); in nv50_gr_init()
953 nv_wr32(priv, 0x400828, 0x00000000); in nv50_gr_init()
954 nv_wr32(priv, 0x40082c, 0x00000000); in nv50_gr_init()
955 nv_wr32(priv, 0x400830, 0x00000000); in nv50_gr_init()
956 nv_wr32(priv, 0x40032c, 0x00000000); in nv50_gr_init()
957 nv_wr32(priv, 0x400330, 0x00000000); in nv50_gr_init()
960 switch (nv_device(priv)->chipset & 0xf0) { in nv50_gr_init()
964 nv_wr32(priv, 0x402ca8, 0x00000800); in nv50_gr_init()
968 if (nv_device(priv)->chipset == 0xa0 || in nv50_gr_init()
969 nv_device(priv)->chipset == 0xaa || in nv50_gr_init()
970 nv_device(priv)->chipset == 0xac) { in nv50_gr_init()
971 nv_wr32(priv, 0x402ca8, 0x00000802); in nv50_gr_init()
973 nv_wr32(priv, 0x402cc0, 0x00000000); in nv50_gr_init()
974 nv_wr32(priv, 0x402ca8, 0x00000002); in nv50_gr_init()
982 nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000); in nv50_gr_init()
983 nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000); in nv50_gr_init()
984 nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000); in nv50_gr_init()
985 nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000); in nv50_gr_init()