Lines Matching refs:nv_wo32
66 nv_wo32(xtensa, 0xc20, intr); in _nvkm_xtensa_intr()
135 nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i)); in _nvkm_xtensa_init()
139 nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */ in _nvkm_xtensa_init()
140 nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */ in _nvkm_xtensa_init()
142 nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */ in _nvkm_xtensa_init()
143 nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ in _nvkm_xtensa_init()
144 nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ in _nvkm_xtensa_init()
146 nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */ in _nvkm_xtensa_init()
147 nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */ in _nvkm_xtensa_init()
148 nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */ in _nvkm_xtensa_init()
151 nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */ in _nvkm_xtensa_init()
153 nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */ in _nvkm_xtensa_init()
155 nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ in _nvkm_xtensa_init()
156 nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ in _nvkm_xtensa_init()
165 nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */ in _nvkm_xtensa_fini()
166 nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */ in _nvkm_xtensa_fini()