48 	struct nv50_bar_priv *priv = (void *)bar;  in nv50_bar_kmap()  local
51 	ret = nvkm_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma);  in nv50_bar_kmap()
63 	struct nv50_bar_priv *priv = (void *)bar;  in nv50_bar_umap()  local
66 	ret = nvkm_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma);  in nv50_bar_umap()
84 	struct nv50_bar_priv *priv = (void *)bar;  in nv50_bar_flush()  local
86 	spin_lock_irqsave(&priv->lock, flags);  in nv50_bar_flush()
87 	nv_wr32(priv, 0x00330c, 0x00000001);  in nv50_bar_flush()
88 	if (!nv_wait(priv, 0x00330c, 0x00000002, 0x00000000))  in nv50_bar_flush()
89 		nv_warn(priv, "flush timeout\n");  in nv50_bar_flush()
90 	spin_unlock_irqrestore(&priv->lock, flags);  in nv50_bar_flush()
96 	struct nv50_bar_priv *priv = (void *)bar;  in g84_bar_flush()  local
98 	spin_lock_irqsave(&priv->lock, flags);  in g84_bar_flush()
100 	if (!nv_wait(priv, 0x070000, 0x00000002, 0x00000000))  in g84_bar_flush()
101 		nv_warn(priv, "flush timeout\n");  in g84_bar_flush()
102 	spin_unlock_irqrestore(&priv->lock, flags);  in g84_bar_flush()
113 	struct nv50_bar_priv *priv;  in nv50_bar_ctor()  local
117 	ret = nvkm_bar_create(parent, engine, oclass, &priv);  in nv50_bar_ctor()
118 	*pobject = nv_object(priv);  in nv50_bar_ctor()
122 	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,  in nv50_bar_ctor()
123 			      NVOBJ_FLAG_HEAP, &priv->mem);  in nv50_bar_ctor()
124 	heap = nv_object(priv->mem);  in nv50_bar_ctor()
128 	ret = nvkm_gpuobj_new(nv_object(priv), heap,  in nv50_bar_ctor()
130 			      0, 0, &priv->pad);  in nv50_bar_ctor()
134 	ret = nvkm_gpuobj_new(nv_object(priv), heap, 0x4000, 0, 0, &priv->pgd);  in nv50_bar_ctor()
148 	ret = nvkm_gpuobj_new(nv_object(priv), heap,  in nv50_bar_ctor()
155 	ret = nvkm_vm_ref(vm, &priv->bar3_vm, priv->pgd);  in nv50_bar_ctor()
160 	ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3);  in nv50_bar_ctor()
164 	nv_wo32(priv->bar3, 0x00, 0x7fc00000);  in nv50_bar_ctor()
165 	nv_wo32(priv->bar3, 0x04, lower_32_bits(limit));  in nv50_bar_ctor()
166 	nv_wo32(priv->bar3, 0x08, lower_32_bits(start));  in nv50_bar_ctor()
167 	nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 |  in nv50_bar_ctor()
169 	nv_wo32(priv->bar3, 0x10, 0x00000000);  in nv50_bar_ctor()
170 	nv_wo32(priv->bar3, 0x14, 0x00000000);  in nv50_bar_ctor()
182 	ret = nvkm_vm_ref(vm, &priv->bar1_vm, priv->pgd);  in nv50_bar_ctor()
187 	ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1);  in nv50_bar_ctor()
191 	nv_wo32(priv->bar1, 0x00, 0x7fc00000);  in nv50_bar_ctor()
192 	nv_wo32(priv->bar1, 0x04, lower_32_bits(limit));  in nv50_bar_ctor()
193 	nv_wo32(priv->bar1, 0x08, lower_32_bits(start));  in nv50_bar_ctor()
194 	nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 |  in nv50_bar_ctor()
196 	nv_wo32(priv->bar1, 0x10, 0x00000000);  in nv50_bar_ctor()
197 	nv_wo32(priv->bar1, 0x14, 0x00000000);  in nv50_bar_ctor()
199 	priv->base.alloc = nvkm_bar_alloc;  in nv50_bar_ctor()
200 	priv->base.kmap = nv50_bar_kmap;  in nv50_bar_ctor()
201 	priv->base.umap = nv50_bar_umap;  in nv50_bar_ctor()
202 	priv->base.unmap = nv50_bar_unmap;  in nv50_bar_ctor()
204 		priv->base.flush = nv50_bar_flush;  in nv50_bar_ctor()
206 		priv->base.flush = g84_bar_flush;  in nv50_bar_ctor()
207 	spin_lock_init(&priv->lock);  in nv50_bar_ctor()
214 	struct nv50_bar_priv *priv = (void *)object;  in nv50_bar_dtor()  local
215 	nvkm_gpuobj_ref(NULL, &priv->bar1);  in nv50_bar_dtor()
216 	nvkm_vm_ref(NULL, &priv->bar1_vm, priv->pgd);  in nv50_bar_dtor()
217 	nvkm_gpuobj_ref(NULL, &priv->bar3);  in nv50_bar_dtor()
218 	if (priv->bar3_vm) {  in nv50_bar_dtor()
219 		nvkm_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]);  in nv50_bar_dtor()
220 		nvkm_vm_ref(NULL, &priv->bar3_vm, priv->pgd);  in nv50_bar_dtor()
222 	nvkm_gpuobj_ref(NULL, &priv->pgd);  in nv50_bar_dtor()
223 	nvkm_gpuobj_ref(NULL, &priv->pad);  in nv50_bar_dtor()
224 	nvkm_gpuobj_ref(NULL, &priv->mem);  in nv50_bar_dtor()
225 	nvkm_bar_destroy(&priv->base);  in nv50_bar_dtor()
231 	struct nv50_bar_priv *priv = (void *)object;  in nv50_bar_init()  local
234 	ret = nvkm_bar_init(&priv->base);  in nv50_bar_init()
238 	nv_mask(priv, 0x000200, 0x00000100, 0x00000000);  in nv50_bar_init()
239 	nv_mask(priv, 0x000200, 0x00000100, 0x00000100);  in nv50_bar_init()
240 	nv_wr32(priv, 0x100c80, 0x00060001);  in nv50_bar_init()
241 	if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) {  in nv50_bar_init()
242 		nv_error(priv, "vm flush timeout\n");  in nv50_bar_init()
246 	nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12);  in nv50_bar_init()
247 	nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12);  in nv50_bar_init()
248 	nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4);  in nv50_bar_init()
249 	nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4);  in nv50_bar_init()
251 		nv_wr32(priv, 0x001900 + (i * 4), 0x00000000);  in nv50_bar_init()
258 	struct nv50_bar_priv *priv = (void *)object;  in nv50_bar_fini()  local
259 	return nvkm_bar_fini(&priv->base, suspend);  in nv50_bar_fini()