41 		u8 pstate, u8 domain, u32 input)  in nvkm_clk_adjust()  argument
61 			if (subd && boostS.domain == domain) {  in nvkm_clk_adjust()
139 	struct nvkm_domain *domain = clk->domains;  in nvkm_cstate_new()  local
156 	while (domain && domain->name != nv_clk_src_max) {  in nvkm_cstate_new()
157 		if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {  in nvkm_cstate_new()
159 						   domain->bios, cstepX.freq);  in nvkm_cstate_new()
160 			cstate->domain[domain->name] = freq;  in nvkm_cstate_new()
162 		domain++;  in nvkm_cstate_new()
188 		int khz = pstate->base.domain[nv_clk_src_mem];  in nvkm_pstate_prog()
259 		u32 lo = pstate->base.domain[clock->name];  in nvkm_pstate_info()
266 			u32 freq = cstate->domain[clock->name];  in nvkm_pstate_info()
305 	struct nvkm_domain *domain = clk->domains - 1;  in nvkm_pstate_new()  local
329 	cstate->domain[nv_clk_src_core] = perfE.core;  in nvkm_pstate_new()
330 	cstate->domain[nv_clk_src_shader] = perfE.shader;  in nvkm_pstate_new()
331 	cstate->domain[nv_clk_src_mem] = perfE.memory;  in nvkm_pstate_new()
332 	cstate->domain[nv_clk_src_vdec] = perfE.vdec;  in nvkm_pstate_new()
333 	cstate->domain[nv_clk_src_dom6] = perfE.disp;  in nvkm_pstate_new()
335 	while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {  in nvkm_pstate_new()
338 		u32 perfSe = nvbios_perfSp(bios, data, domain->bios,  in nvkm_pstate_new()
343 		if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {  in nvkm_pstate_new()
346 							 domain->bios,  in nvkm_pstate_new()
350 		cstate->domain[domain->name] = perfS.v40.freq;  in nvkm_pstate_new()
502 		clk->bstate.base.domain[clock->name] = ret;  in _nvkm_clk_init()