Lines Matching refs:priv
129 gk20a_pllg_read_mnp(struct gk20a_clk_priv *priv) in gk20a_pllg_read_mnp() argument
133 val = nv_rd32(priv, GPCPLL_COEFF); in gk20a_pllg_read_mnp()
134 priv->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
135 priv->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
136 priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
140 gk20a_pllg_calc_rate(struct gk20a_clk_priv *priv) in gk20a_pllg_calc_rate() argument
145 rate = priv->parent_rate * priv->n; in gk20a_pllg_calc_rate()
146 divider = priv->m * pl_to_div[priv->pl]; in gk20a_pllg_calc_rate()
153 gk20a_pllg_calc_mnp(struct gk20a_clk_priv *priv, unsigned long rate) in gk20a_pllg_calc_mnp() argument
166 ref_clk_f = priv->parent_rate / MHZ; in gk20a_pllg_calc_mnp()
168 max_vco_f = priv->params->max_vco; in gk20a_pllg_calc_mnp()
169 min_vco_f = priv->params->min_vco; in gk20a_pllg_calc_mnp()
170 best_m = priv->params->max_m; in gk20a_pllg_calc_mnp()
171 best_n = priv->params->min_n; in gk20a_pllg_calc_mnp()
172 best_pl = priv->params->min_pl; in gk20a_pllg_calc_mnp()
180 high_pl = min(high_pl, priv->params->max_pl); in gk20a_pllg_calc_mnp()
181 high_pl = max(high_pl, priv->params->min_pl); in gk20a_pllg_calc_mnp()
185 low_pl = min(low_pl, priv->params->max_pl); in gk20a_pllg_calc_mnp()
186 low_pl = max(low_pl, priv->params->min_pl); in gk20a_pllg_calc_mnp()
202 nv_debug(priv, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, in gk20a_pllg_calc_mnp()
208 for (m = priv->params->min_m; m <= priv->params->max_m; m++) { in gk20a_pllg_calc_mnp()
211 if (u_f < priv->params->min_u) in gk20a_pllg_calc_mnp()
213 if (u_f > priv->params->max_u) in gk20a_pllg_calc_mnp()
219 if (n > priv->params->max_n) in gk20a_pllg_calc_mnp()
223 if (n < priv->params->min_n) in gk20a_pllg_calc_mnp()
225 if (n > priv->params->max_n) in gk20a_pllg_calc_mnp()
253 nv_debug(priv, "no best match for target @ %dMHz on gpc_pll", in gk20a_pllg_calc_mnp()
256 priv->m = best_m; in gk20a_pllg_calc_mnp()
257 priv->n = best_n; in gk20a_pllg_calc_mnp()
258 priv->pl = best_pl; in gk20a_pllg_calc_mnp()
260 target_freq = gk20a_pllg_calc_rate(priv) / MHZ; in gk20a_pllg_calc_mnp()
262 nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", in gk20a_pllg_calc_mnp()
263 target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]); in gk20a_pllg_calc_mnp()
268 gk20a_pllg_slide(struct gk20a_clk_priv *priv, u32 n) in gk20a_pllg_slide() argument
274 val = nv_rd32(priv, GPCPLL_COEFF); in gk20a_pllg_slide()
280 nv_mask(priv, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, in gk20a_pllg_slide()
282 nv_mask(priv, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, in gk20a_pllg_slide()
286 nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, in gk20a_pllg_slide()
291 val = nv_rd32(priv, GPCPLL_COEFF); in gk20a_pllg_slide()
295 nv_wr32(priv, GPCPLL_COEFF, val); in gk20a_pllg_slide()
298 val = nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); in gk20a_pllg_slide()
301 nv_wr32(priv, GPCPLL_NDIV_SLOWDOWN, val); in gk20a_pllg_slide()
305 val = nv_rd32(priv, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); in gk20a_pllg_slide()
311 nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, in gk20a_pllg_slide()
314 nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); in gk20a_pllg_slide()
317 nv_error(priv, "gpcpll dynamic ramp timeout\n"); in gk20a_pllg_slide()
325 _gk20a_pllg_enable(struct gk20a_clk_priv *priv) in _gk20a_pllg_enable() argument
327 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); in _gk20a_pllg_enable()
328 nv_rd32(priv, GPCPLL_CFG); in _gk20a_pllg_enable()
332 _gk20a_pllg_disable(struct gk20a_clk_priv *priv) in _gk20a_pllg_disable() argument
334 nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); in _gk20a_pllg_disable()
335 nv_rd32(priv, GPCPLL_CFG); in _gk20a_pllg_disable()
339 _gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv, bool allow_slide) in _gk20a_pllg_program_mnp() argument
345 val = nv_rd32(priv, GPCPLL_COEFF); in _gk20a_pllg_program_mnp()
350 cfg = nv_rd32(priv, GPCPLL_CFG); in _gk20a_pllg_program_mnp()
351 if (allow_slide && priv->m == m_old && priv->pl == pl_old && in _gk20a_pllg_program_mnp()
353 return gk20a_pllg_slide(priv, priv->n); in _gk20a_pllg_program_mnp()
357 n_lo = DIV_ROUND_UP(m_old * priv->params->min_vco, in _gk20a_pllg_program_mnp()
358 priv->parent_rate / MHZ); in _gk20a_pllg_program_mnp()
360 int ret = gk20a_pllg_slide(priv, n_lo); in _gk20a_pllg_program_mnp()
367 nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, in _gk20a_pllg_program_mnp()
371 val = nv_rd32(priv, SEL_VCO); in _gk20a_pllg_program_mnp()
374 nv_wr32(priv, SEL_VCO, val); in _gk20a_pllg_program_mnp()
377 val = nv_rd32(priv, GPCPLL_CFG); in _gk20a_pllg_program_mnp()
380 nv_wr32(priv, GPCPLL_CFG, val); in _gk20a_pllg_program_mnp()
381 nv_rd32(priv, GPCPLL_CFG); in _gk20a_pllg_program_mnp()
385 _gk20a_pllg_disable(priv); in _gk20a_pllg_program_mnp()
387 nv_debug(priv, "%s: m=%d n=%d pl=%d\n", __func__, priv->m, priv->n, in _gk20a_pllg_program_mnp()
388 priv->pl); in _gk20a_pllg_program_mnp()
390 n_lo = DIV_ROUND_UP(priv->m * priv->params->min_vco, in _gk20a_pllg_program_mnp()
391 priv->parent_rate / MHZ); in _gk20a_pllg_program_mnp()
392 val = priv->m << GPCPLL_COEFF_M_SHIFT; in _gk20a_pllg_program_mnp()
393 val |= (allow_slide ? n_lo : priv->n) << GPCPLL_COEFF_N_SHIFT; in _gk20a_pllg_program_mnp()
394 val |= priv->pl << GPCPLL_COEFF_P_SHIFT; in _gk20a_pllg_program_mnp()
395 nv_wr32(priv, GPCPLL_COEFF, val); in _gk20a_pllg_program_mnp()
397 _gk20a_pllg_enable(priv); in _gk20a_pllg_program_mnp()
399 val = nv_rd32(priv, GPCPLL_CFG); in _gk20a_pllg_program_mnp()
402 nv_wr32(priv, GPCPLL_CFG, val); in _gk20a_pllg_program_mnp()
405 if (!nvkm_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, in _gk20a_pllg_program_mnp()
407 nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__); in _gk20a_pllg_program_mnp()
412 nv_mask(priv, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); in _gk20a_pllg_program_mnp()
415 val = nv_rd32(priv, GPC2CLK_OUT); in _gk20a_pllg_program_mnp()
418 nv_wr32(priv, GPC2CLK_OUT, val); in _gk20a_pllg_program_mnp()
421 return allow_slide ? gk20a_pllg_slide(priv, priv->n) : 0; in _gk20a_pllg_program_mnp()
425 gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv) in gk20a_pllg_program_mnp() argument
429 err = _gk20a_pllg_program_mnp(priv, true); in gk20a_pllg_program_mnp()
431 err = _gk20a_pllg_program_mnp(priv, false); in gk20a_pllg_program_mnp()
437 gk20a_pllg_disable(struct gk20a_clk_priv *priv) in gk20a_pllg_disable() argument
442 val = nv_rd32(priv, GPCPLL_CFG); in gk20a_pllg_disable()
446 coeff = nv_rd32(priv, GPCPLL_COEFF); in gk20a_pllg_disable()
448 n_lo = DIV_ROUND_UP(m * priv->params->min_vco, in gk20a_pllg_disable()
449 priv->parent_rate / MHZ); in gk20a_pllg_disable()
450 gk20a_pllg_slide(priv, n_lo); in gk20a_pllg_disable()
454 nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); in gk20a_pllg_disable()
456 _gk20a_pllg_disable(priv); in gk20a_pllg_disable()
565 struct gk20a_clk_priv *priv = (void *)clk; in gk20a_clk_read() local
571 gk20a_pllg_read_mnp(priv); in gk20a_clk_read()
572 return gk20a_pllg_calc_rate(priv) / GK20A_CLK_GPC_MDIV; in gk20a_clk_read()
582 struct gk20a_clk_priv *priv = (void *)clk; in gk20a_clk_calc() local
584 return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] * in gk20a_clk_calc()
591 struct gk20a_clk_priv *priv = (void *)clk; in gk20a_clk_prog() local
593 return gk20a_pllg_program_mnp(priv); in gk20a_clk_prog()
604 struct gk20a_clk_priv *priv = (void *)object; in gk20a_clk_fini() local
607 ret = nvkm_clk_fini(&priv->base, false); in gk20a_clk_fini()
609 gk20a_pllg_disable(priv); in gk20a_clk_fini()
617 struct gk20a_clk_priv *priv = (void *)object; in gk20a_clk_init() local
620 nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); in gk20a_clk_init()
622 ret = nvkm_clk_init(&priv->base); in gk20a_clk_init()
626 ret = gk20a_clk_prog(&priv->base); in gk20a_clk_init()
628 nv_error(priv, "cannot initialize clock\n"); in gk20a_clk_init()
640 struct gk20a_clk_priv *priv; in gk20a_clk_ctor() local
653 true, &priv); in gk20a_clk_ctor()
654 *pobject = nv_object(priv); in gk20a_clk_ctor()
658 priv->params = &gk20a_pllg_params; in gk20a_clk_ctor()
661 priv->parent_rate = clk_get_rate(plat->gpu->clk); in gk20a_clk_ctor()
662 nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ); in gk20a_clk_ctor()
664 priv->base.read = gk20a_clk_read; in gk20a_clk_ctor()
665 priv->base.calc = gk20a_clk_calc; in gk20a_clk_ctor()
666 priv->base.prog = gk20a_clk_prog; in gk20a_clk_ctor()
667 priv->base.tidy = gk20a_clk_tidy; in gk20a_clk_ctor()