106 read_pll(struct gt215_clk_priv *priv, int clk, u32 pll)  in read_pll()  argument
108 	u32 ctrl = nv_rd32(priv, pll + 0);  in read_pll()
113 			u32 coef = nv_rd32(priv, pll + 4);  in read_pll()
121 			if ((pll & 0x00ff00) == 0x00e800)  in read_pll()
226 gt215_pll_info(struct nvkm_clk *clock, int clk, u32 pll, u32 khz,  in gt215_pll_info()  argument
235 	info->pll = 0;  in gt215_pll_info()
241 	if (!pll || (diff >= -2000 && diff < 3000)) {  in gt215_pll_info()
246 	ret = nvbios_pll_parse(bios, pll, &limits);  in gt215_pll_info()
256 		info->pll = (P << 16) | (N << 8) | M;  in gt215_pll_info()
266 	 int clk, u32 pll, int idx)  in calc_clk()  argument
268 	int ret = gt215_pll_info(&priv->base, clk, pll, cstate->domain[idx],  in calc_clk()
340 prog_pll(struct gt215_clk_priv *priv, int clk, u32 pll, int idx)  in prog_pll()  argument
345 	const u32 ctrl = pll + 0;  in prog_pll()
346 	const u32 coef = pll + 4;  in prog_pll()
349 	if (info->pll) {  in prog_pll()
359 		nv_wr32(priv, coef, info->pll);  in prog_pll()
444 	if (core->pll) {  in gt215_clk_calc()
468 	if (core->pll)  in gt215_clk_prog()