143 	      struct nvkm_pll_vals *pv)  in setPLL_single()  argument
148 	uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;  in setPLL_single()
162 	if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))  in setPLL_single()
164 		nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff));  in setPLL_single()
167 		nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1);  in setPLL_single()
197 		       struct nvkm_pll_vals *pv)  in setPLL_double_highregs()  argument
204 	uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;  in setPLL_double_highregs()
205 	uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;  in setPLL_double_highregs()
207 	bool single_stage = !pv->NM2 || pv->N2 == pv->M2;	/* nv41+ only */  in setPLL_double_highregs()
213 		pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |  in setPLL_double_highregs()
214 		       (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;  in setPLL_double_highregs()
274 		      struct nvkm_pll_vals *pv)  in setPLL_double_lowregs()  argument
287 	uint32_t NMNM = pv->NM2 << 16 | pv->NM1;  in setPLL_double_lowregs()
289 			0xc << 28 | pv->log2P << 16;  in setPLL_double_lowregs()
293 	bool single_stage = !pv->NM2 || pv->N2 == pv->M2;  in setPLL_double_lowregs()
310 		Pval2 = pv->log2P + info.bias_p;  in setPLL_double_lowregs()
356 	struct nvkm_pll_vals pv;  in nv04_devinit_pll_set()  local
371 	pv.refclk = info.refclk;  in nv04_devinit_pll_set()
372 	pv.N1 = N1;  in nv04_devinit_pll_set()
373 	pv.M1 = M1;  in nv04_devinit_pll_set()
374 	pv.N2 = N2;  in nv04_devinit_pll_set()
375 	pv.M2 = M2;  in nv04_devinit_pll_set()
376 	pv.log2P = P;  in nv04_devinit_pll_set()
381 			setPLL_double_highregs(devinit, type, &pv);  in nv04_devinit_pll_set()
383 			setPLL_double_lowregs(devinit, type, &pv);  in nv04_devinit_pll_set()
385 		setPLL_single(devinit, type, &pv);  in nv04_devinit_pll_set()