Lines Matching refs:pte
40 dma_addr_t *list, u32 pte, u32 cnt) in nv44_vm_fill() argument
42 u32 base = (pte << 2) & ~0x0000000f; in nv44_vm_fill()
52 switch (pte++ & 0x3) { in nv44_vm_fill()
86 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) in nv44_vm_map_sg() argument
92 if (pte & 3) { in nv44_vm_map_sg()
93 u32 max = 4 - (pte & 3); in nv44_vm_map_sg()
95 nv44_vm_fill(pgt, priv->null, list, pte, part); in nv44_vm_map_sg()
96 pte += part; in nv44_vm_map_sg()
104 nv_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27); in nv44_vm_map_sg()
105 nv_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22); in nv44_vm_map_sg()
106 nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17); in nv44_vm_map_sg()
107 nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000); in nv44_vm_map_sg()
112 nv44_vm_fill(pgt, priv->null, list, pte, cnt); in nv44_vm_map_sg()
116 nv44_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) in nv44_vm_unmap() argument
120 if (pte & 3) { in nv44_vm_unmap()
121 u32 max = 4 - (pte & 3); in nv44_vm_unmap()
123 nv44_vm_fill(pgt, priv->null, NULL, pte, part); in nv44_vm_unmap()
124 pte += part; in nv44_vm_unmap()
129 nv_wo32(pgt, pte++ * 4, 0x00000000); in nv44_vm_unmap()
130 nv_wo32(pgt, pte++ * 4, 0x00000000); in nv44_vm_unmap()
131 nv_wo32(pgt, pte++ * 4, 0x00000000); in nv44_vm_unmap()
132 nv_wo32(pgt, pte++ * 4, 0x00000000); in nv44_vm_unmap()
137 nv44_vm_fill(pgt, priv->null, NULL, pte, cnt); in nv44_vm_unmap()