31 	struct nv04_timer_priv *priv = (void *)ptimer;  in nv04_timer_read()  local
35 		hi = nv_rd32(priv, NV04_PTIMER_TIME_1);  in nv04_timer_read()
36 		lo = nv_rd32(priv, NV04_PTIMER_TIME_0);  in nv04_timer_read()
37 	} while (hi != nv_rd32(priv, NV04_PTIMER_TIME_1));  in nv04_timer_read()
45 	struct nv04_timer_priv *priv = (void *)ptimer;  in nv04_timer_alarm_trigger()  local
51 	spin_lock_irqsave(&priv->lock, flags);  in nv04_timer_alarm_trigger()
52 	list_for_each_entry_safe(alarm, atemp, &priv->alarms, head) {  in nv04_timer_alarm_trigger()
58 	if (!list_empty(&priv->alarms)) {  in nv04_timer_alarm_trigger()
59 		alarm = list_first_entry(&priv->alarms, typeof(*alarm), head);  in nv04_timer_alarm_trigger()
60 		nv_wr32(priv, NV04_PTIMER_ALARM_0, alarm->timestamp);  in nv04_timer_alarm_trigger()
61 		nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000001);  in nv04_timer_alarm_trigger()
63 		nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);  in nv04_timer_alarm_trigger()
65 	spin_unlock_irqrestore(&priv->lock, flags);  in nv04_timer_alarm_trigger()
77 	struct nv04_timer_priv *priv = (void *)ptimer;  in nv04_timer_alarm()  local
84 	spin_lock_irqsave(&priv->lock, flags);  in nv04_timer_alarm()
89 		list_for_each_entry(list, &priv->alarms, head) {  in nv04_timer_alarm()
95 	spin_unlock_irqrestore(&priv->lock, flags);  in nv04_timer_alarm()
104 	struct nv04_timer_priv *priv = (void *)ptimer;  in nv04_timer_alarm_cancel()  local
106 	spin_lock_irqsave(&priv->lock, flags);  in nv04_timer_alarm_cancel()
108 	spin_unlock_irqrestore(&priv->lock, flags);  in nv04_timer_alarm_cancel()
114 	struct nv04_timer_priv *priv = (void *)subdev;  in nv04_timer_intr()  local
115 	u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0);  in nv04_timer_intr()
118 		nv04_timer_alarm_trigger(&priv->base);  in nv04_timer_intr()
119 		nv_wr32(priv, NV04_PTIMER_INTR_0, 0x00000001);  in nv04_timer_intr()
124 		nv_error(priv, "unknown stat 0x%08x\n", stat);  in nv04_timer_intr()
125 		nv_wr32(priv, NV04_PTIMER_INTR_0, stat);  in nv04_timer_intr()
132 	struct nv04_timer_priv *priv = (void *)object;  in nv04_timer_fini()  local
134 		priv->suspend_time = nv04_timer_read(&priv->base);  in nv04_timer_fini()
135 	nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);  in nv04_timer_fini()
136 	return nvkm_timer_fini(&priv->base, suspend);  in nv04_timer_fini()
143 	struct nv04_timer_priv *priv = (void *)object;  in nv04_timer_init()  local
147 	ret = nvkm_timer_init(&priv->base);  in nv04_timer_init()
172 		nv_wr32(priv, 0x009220, m - 1);  in nv04_timer_init()
176 		nv_warn(priv, "unknown input clock freq\n");  in nv04_timer_init()
177 		if (!nv_rd32(priv, NV04_PTIMER_NUMERATOR) ||  in nv04_timer_init()
178 		    !nv_rd32(priv, NV04_PTIMER_DENOMINATOR)) {  in nv04_timer_init()
179 			nv_wr32(priv, NV04_PTIMER_NUMERATOR, 1);  in nv04_timer_init()
180 			nv_wr32(priv, NV04_PTIMER_DENOMINATOR, 1);  in nv04_timer_init()
202 	lo = priv->suspend_time;  in nv04_timer_init()
203 	hi = (priv->suspend_time >> 32);  in nv04_timer_init()
205 	nv_debug(priv, "input frequency : %dHz\n", f);  in nv04_timer_init()
206 	nv_debug(priv, "input multiplier: %d\n", m);  in nv04_timer_init()
207 	nv_debug(priv, "numerator       : 0x%08x\n", n);  in nv04_timer_init()
208 	nv_debug(priv, "denominator     : 0x%08x\n", d);  in nv04_timer_init()
209 	nv_debug(priv, "timer frequency : %dHz\n", (f * m) * d / n);  in nv04_timer_init()
210 	nv_debug(priv, "time low        : 0x%08x\n", lo);  in nv04_timer_init()
211 	nv_debug(priv, "time high       : 0x%08x\n", hi);  in nv04_timer_init()
213 	nv_wr32(priv, NV04_PTIMER_NUMERATOR, n);  in nv04_timer_init()
214 	nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d);  in nv04_timer_init()
215 	nv_wr32(priv, NV04_PTIMER_INTR_0, 0xffffffff);  in nv04_timer_init()
216 	nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);  in nv04_timer_init()
217 	nv_wr32(priv, NV04_PTIMER_TIME_1, hi);  in nv04_timer_init()
218 	nv_wr32(priv, NV04_PTIMER_TIME_0, lo);  in nv04_timer_init()
225 	struct nv04_timer_priv *priv = (void *)object;  in nv04_timer_dtor()  local
226 	return nvkm_timer_destroy(&priv->base);  in nv04_timer_dtor()
234 	struct nv04_timer_priv *priv;  in nv04_timer_ctor()  local
237 	ret = nvkm_timer_create(parent, engine, oclass, &priv);  in nv04_timer_ctor()
238 	*pobject = nv_object(priv);  in nv04_timer_ctor()
242 	priv->base.base.intr = nv04_timer_intr;  in nv04_timer_ctor()
243 	priv->base.read = nv04_timer_read;  in nv04_timer_ctor()
244 	priv->base.alarm = nv04_timer_alarm;  in nv04_timer_ctor()
245 	priv->base.alarm_cancel = nv04_timer_alarm_cancel;  in nv04_timer_ctor()
246 	priv->suspend_time = 0;  in nv04_timer_ctor()
248 	INIT_LIST_HEAD(&priv->alarms);  in nv04_timer_ctor()
249 	spin_lock_init(&priv->lock);  in nv04_timer_ctor()