1375 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1377 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1379 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1381 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1383 	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in dce4_crtc_do_set_base()
1384 	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in dce4_crtc_do_set_base()
1391 	WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1398 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1399 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1400 	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1401 	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1402 	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);  in dce4_crtc_do_set_base()
1403 	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);  in dce4_crtc_do_set_base()
1406 	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);  in dce4_crtc_do_set_base()
1407 	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);  in dce4_crtc_do_set_base()
1410 		WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1413 		WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1417 	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1424 	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1429 	tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);  in dce4_crtc_do_set_base()
1431 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_crtc_do_set_base()
1434 	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);  in dce4_crtc_do_set_base()
1590 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1593 	       radeon_crtc->crtc_offset, (u32) fb_location);  in avivo_crtc_do_set_base()
1594 	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in avivo_crtc_do_set_base()
1596 		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in avivo_crtc_do_set_base()
1599 	WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1605 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1606 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1607 	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1608 	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1609 	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);  in avivo_crtc_do_set_base()
1610 	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);  in avivo_crtc_do_set_base()
1613 	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);  in avivo_crtc_do_set_base()
1614 	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);  in avivo_crtc_do_set_base()
1616 	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1620 	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1624 	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1629 	tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);  in avivo_crtc_do_set_base()
1631 	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);  in avivo_crtc_do_set_base()
1634 	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);  in avivo_crtc_do_set_base()
2150 		WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);  in atombios_crtc_disable()
2152 		WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);  in atombios_crtc_disable()
2216 			radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2219 			radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2222 			radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2225 			radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2228 			radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2231 			radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2236 			radeon_crtc->crtc_offset =  in radeon_atombios_init_crtc()
2239 			radeon_crtc->crtc_offset = 0;  in radeon_atombios_init_crtc()