40 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_overscan_setup()  local
47 	args.ucCRTC = radeon_crtc->crtc_id;  in atombios_overscan_setup()
49 	switch (radeon_crtc->rmx_type) {  in atombios_overscan_setup()
70 		args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);  in atombios_overscan_setup()
71 		args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);  in atombios_overscan_setup()
72 		args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);  in atombios_overscan_setup()
73 		args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);  in atombios_overscan_setup()
83 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_scaler_setup()  local
87 		to_radeon_encoder(radeon_crtc->encoder);  in atombios_scaler_setup()
92 	if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)  in atombios_scaler_setup()
103 	args.ucScaler = radeon_crtc->crtc_id;  in atombios_scaler_setup()
138 		switch (radeon_crtc->rmx_type) {  in atombios_scaler_setup()
159 		atom_rv515_force_tv_scaler(rdev, radeon_crtc);  in atombios_scaler_setup()
165 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_lock_crtc()  local
174 	args.ucCRTC = radeon_crtc->crtc_id;  in atombios_lock_crtc()
182 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_enable_crtc()  local
190 	args.ucCRTC = radeon_crtc->crtc_id;  in atombios_enable_crtc()
198 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_enable_crtc_memreq()  local
206 	args.ucCRTC = radeon_crtc->crtc_id;  in atombios_enable_crtc_memreq()
224 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_blank_crtc()  local
234 		vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);  in atombios_blank_crtc()
235 		WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);  in atombios_blank_crtc()
238 	args.ucCRTC = radeon_crtc->crtc_id;  in atombios_blank_crtc()
244 		WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);  in atombios_blank_crtc()
250 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_powergate_crtc()  local
258 	args.ucDispPipeId = radeon_crtc->crtc_id;  in atombios_powergate_crtc()
268 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_crtc_dpms()  local
272 		radeon_crtc->enabled = true;  in atombios_crtc_dpms()
277 		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);  in atombios_crtc_dpms()
283 		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);  in atombios_crtc_dpms()
284 		if (radeon_crtc->enabled)  in atombios_crtc_dpms()
289 		radeon_crtc->enabled = false;  in atombios_crtc_dpms()
300 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_set_crtc_dtd_timing()  local
308 	args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));  in atombios_set_crtc_dtd_timing()
310 		cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));  in atombios_set_crtc_dtd_timing()
311 	args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));  in atombios_set_crtc_dtd_timing()
313 		cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));  in atombios_set_crtc_dtd_timing()
315 		cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);  in atombios_set_crtc_dtd_timing()
319 		cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);  in atombios_set_crtc_dtd_timing()
322 	args.ucH_Border = radeon_crtc->h_border;  in atombios_set_crtc_dtd_timing()
323 	args.ucV_Border = radeon_crtc->v_border;  in atombios_set_crtc_dtd_timing()
339 	args.ucCRTC = radeon_crtc->crtc_id;  in atombios_set_crtc_dtd_timing()
347 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_crtc_set_timing()  local
366 	args.ucOverscanRight = radeon_crtc->h_border;  in atombios_crtc_set_timing()
367 	args.ucOverscanLeft = radeon_crtc->h_border;  in atombios_crtc_set_timing()
368 	args.ucOverscanBottom = radeon_crtc->v_border;  in atombios_crtc_set_timing()
369 	args.ucOverscanTop = radeon_crtc->v_border;  in atombios_crtc_set_timing()
385 	args.ucCRTC = radeon_crtc->crtc_id;  in atombios_crtc_set_timing()
555 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_adjust_pll()  local
558 	struct drm_encoder *encoder = radeon_crtc->encoder;  in atombios_adjust_pll()
565 	int bpc = radeon_crtc->bpc;  in atombios_adjust_pll()
569 	radeon_crtc->pll_flags = 0;  in atombios_adjust_pll()
575 			radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/  in atombios_adjust_pll()
579 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;  in atombios_adjust_pll()
581 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;  in atombios_adjust_pll()
584 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;  in atombios_adjust_pll()
587 			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;  in atombios_adjust_pll()
590 			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;  in atombios_adjust_pll()
592 			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;  in atombios_adjust_pll()
594 		radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;  in atombios_adjust_pll()
597 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;  in atombios_adjust_pll()
599 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;  in atombios_adjust_pll()
622 		if (radeon_crtc->ss_enabled) {  in atombios_adjust_pll()
623 			if (radeon_crtc->ss.refdiv) {  in atombios_adjust_pll()
624 				radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;  in atombios_adjust_pll()
625 				radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;  in atombios_adjust_pll()
627 					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;  in atombios_adjust_pll()
637 			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;  in atombios_adjust_pll()
639 			radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;  in atombios_adjust_pll()
642 			radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;  in atombios_adjust_pll()
644 			radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;  in atombios_adjust_pll()
689 				if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)  in atombios_adjust_pll()
702 				if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)  in atombios_adjust_pll()
730 					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;  in atombios_adjust_pll()
731 					radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;  in atombios_adjust_pll()
732 					radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;  in atombios_adjust_pll()
735 					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;  in atombios_adjust_pll()
736 					radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;  in atombios_adjust_pll()
737 					radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;  in atombios_adjust_pll()
956 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_crtc_prepare_pll()  local
960 		to_radeon_encoder(radeon_crtc->encoder);  in atombios_crtc_prepare_pll()
961 	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);  in atombios_crtc_prepare_pll()
963 	radeon_crtc->bpc = 8;  in atombios_crtc_prepare_pll()
964 	radeon_crtc->ss_enabled = false;  in atombios_crtc_prepare_pll()
969 	    (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {  in atombios_crtc_prepare_pll()
972 			radeon_get_connector_for_encoder(radeon_crtc->encoder);  in atombios_crtc_prepare_pll()
981 		radeon_crtc->bpc = radeon_get_monitor_bpc(connector);  in atombios_crtc_prepare_pll()
989 				radeon_crtc->ss_enabled =  in atombios_crtc_prepare_pll()
990 					radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,  in atombios_crtc_prepare_pll()
995 					radeon_crtc->ss_enabled =  in atombios_crtc_prepare_pll()
997 										 &radeon_crtc->ss,  in atombios_crtc_prepare_pll()
999 					if (!radeon_crtc->ss_enabled)  in atombios_crtc_prepare_pll()
1000 						radeon_crtc->ss_enabled =  in atombios_crtc_prepare_pll()
1002 											 &radeon_crtc->ss,  in atombios_crtc_prepare_pll()
1005 					radeon_crtc->ss_enabled =  in atombios_crtc_prepare_pll()
1007 										 &radeon_crtc->ss,  in atombios_crtc_prepare_pll()
1011 				radeon_crtc->ss_enabled = false;  in atombios_crtc_prepare_pll()
1016 				radeon_crtc->ss_enabled =  in atombios_crtc_prepare_pll()
1018 									 &radeon_crtc->ss,  in atombios_crtc_prepare_pll()
1022 				radeon_crtc->ss_enabled =  in atombios_crtc_prepare_pll()
1024 									 &radeon_crtc->ss,  in atombios_crtc_prepare_pll()
1029 				radeon_crtc->ss_enabled =  in atombios_crtc_prepare_pll()
1031 									 &radeon_crtc->ss,  in atombios_crtc_prepare_pll()
1037 				radeon_crtc->ss_enabled =  in atombios_crtc_prepare_pll()
1039 									 &radeon_crtc->ss,  in atombios_crtc_prepare_pll()
1049 	radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);  in atombios_crtc_prepare_pll()
1056 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_crtc_set_pll()  local
1060 		to_radeon_encoder(radeon_crtc->encoder);  in atombios_crtc_set_pll()
1065 	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);  in atombios_crtc_set_pll()
1070 	    (radeon_crtc->bpc > 8))  in atombios_crtc_set_pll()
1071 		clock = radeon_crtc->adjusted_clock;  in atombios_crtc_set_pll()
1073 	switch (radeon_crtc->pll_id) {  in atombios_crtc_set_pll()
1088 	pll->flags = radeon_crtc->pll_flags;  in atombios_crtc_set_pll()
1089 	pll->reference_div = radeon_crtc->pll_reference_div;  in atombios_crtc_set_pll()
1090 	pll->post_div = radeon_crtc->pll_post_div;  in atombios_crtc_set_pll()
1094 		radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,  in atombios_crtc_set_pll()
1097 		radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,  in atombios_crtc_set_pll()
1100 		radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,  in atombios_crtc_set_pll()
1103 	atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,  in atombios_crtc_set_pll()
1104 				 radeon_crtc->crtc_id, &radeon_crtc->ss);  in atombios_crtc_set_pll()
1106 	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,  in atombios_crtc_set_pll()
1109 				  radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);  in atombios_crtc_set_pll()
1111 	if (radeon_crtc->ss_enabled) {  in atombios_crtc_set_pll()
1116 				      (u32)radeon_crtc->ss.percentage) /  in atombios_crtc_set_pll()
1117 				(100 * (u32)radeon_crtc->ss.percentage_divider);  in atombios_crtc_set_pll()
1118 			radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;  in atombios_crtc_set_pll()
1119 			radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &  in atombios_crtc_set_pll()
1121 			if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)  in atombios_crtc_set_pll()
1122 				step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /  in atombios_crtc_set_pll()
1125 				step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /  in atombios_crtc_set_pll()
1127 			radeon_crtc->ss.step = step_size;  in atombios_crtc_set_pll()
1130 		atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,  in atombios_crtc_set_pll()
1131 					 radeon_crtc->crtc_id, &radeon_crtc->ss);  in atombios_crtc_set_pll()
1139 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in dce4_crtc_do_set_base()  local
1352 	switch (radeon_crtc->crtc_id) {  in dce4_crtc_do_set_base()
1375 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1377 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1379 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1381 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1383 	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in dce4_crtc_do_set_base()
1384 	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in dce4_crtc_do_set_base()
1391 	WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1398 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1399 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1400 	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1401 	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1402 	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);  in dce4_crtc_do_set_base()
1403 	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);  in dce4_crtc_do_set_base()
1406 	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);  in dce4_crtc_do_set_base()
1407 	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);  in dce4_crtc_do_set_base()
1410 		WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1413 		WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1417 	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1424 	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1429 	tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);  in dce4_crtc_do_set_base()
1431 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_crtc_do_set_base()
1434 	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);  in dce4_crtc_do_set_base()
1456 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in avivo_crtc_do_set_base()  local
1576 	if (radeon_crtc->crtc_id == 0)  in avivo_crtc_do_set_base()
1582 		if (radeon_crtc->crtc_id) {  in avivo_crtc_do_set_base()
1590 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1593 	       radeon_crtc->crtc_offset, (u32) fb_location);  in avivo_crtc_do_set_base()
1594 	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in avivo_crtc_do_set_base()
1596 		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in avivo_crtc_do_set_base()
1599 	WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1605 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1606 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1607 	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1608 	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1609 	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);  in avivo_crtc_do_set_base()
1610 	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);  in avivo_crtc_do_set_base()
1613 	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);  in avivo_crtc_do_set_base()
1614 	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);  in avivo_crtc_do_set_base()
1616 	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1620 	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1624 	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1629 	tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);  in avivo_crtc_do_set_base()
1631 	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);  in avivo_crtc_do_set_base()
1634 	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);  in avivo_crtc_do_set_base()
1686 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in radeon_legacy_atom_fixup()  local
1689 	switch (radeon_crtc->crtc_id) {  in radeon_legacy_atom_fixup()
1716 	struct radeon_crtc *test_radeon_crtc;  in radeon_get_pll_use_mask()
1743 	struct radeon_crtc *test_radeon_crtc;  in radeon_get_shared_dp_ppll()
1770 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in radeon_get_shared_nondp_ppll()  local
1773 	struct radeon_crtc *test_radeon_crtc;  in radeon_get_shared_nondp_ppll()
1776 	adjusted_clock = radeon_crtc->adjusted_clock;  in radeon_get_shared_nondp_ppll()
1788 			if (test_radeon_crtc->connector == radeon_crtc->connector) {  in radeon_get_shared_nondp_ppll()
1797 			    (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&  in radeon_get_shared_nondp_ppll()
1844 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in radeon_atom_pick_pll()  local
1848 		to_radeon_encoder(radeon_crtc->encoder);  in radeon_atom_pick_pll()
1853 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {  in radeon_atom_pick_pll()
1900 		else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {  in radeon_atom_pick_pll()
1927 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {  in radeon_atom_pick_pll()
1950 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {  in radeon_atom_pick_pll()
1996 		return radeon_crtc->crtc_id;  in radeon_atom_pick_pll()
2025 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_crtc_mode_set()  local
2029 		to_radeon_encoder(radeon_crtc->encoder);  in atombios_crtc_mode_set()
2036 	if (!radeon_crtc->adjusted_clock)  in atombios_crtc_mode_set()
2050 		if (radeon_crtc->crtc_id == 0)  in atombios_crtc_mode_set()
2059 	radeon_crtc->hw_mode = *adjusted_mode;  in atombios_crtc_mode_set()
2068 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_crtc_mode_fixup()  local
2075 			radeon_crtc->encoder = encoder;  in atombios_crtc_mode_fixup()
2076 			radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);  in atombios_crtc_mode_fixup()
2080 	if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {  in atombios_crtc_mode_fixup()
2081 		radeon_crtc->encoder = NULL;  in atombios_crtc_mode_fixup()
2082 		radeon_crtc->connector = NULL;  in atombios_crtc_mode_fixup()
2085 	if (radeon_crtc->encoder) {  in atombios_crtc_mode_fixup()
2087 			to_radeon_encoder(radeon_crtc->encoder);  in atombios_crtc_mode_fixup()
2089 		radeon_crtc->output_csc = radeon_encoder->output_csc;  in atombios_crtc_mode_fixup()
2096 	radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);  in atombios_crtc_mode_fixup()
2098 	if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&  in atombios_crtc_mode_fixup()
2099 	    !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))  in atombios_crtc_mode_fixup()
2126 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);  in atombios_crtc_disable()  local
2150 		WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);  in atombios_crtc_disable()
2152 		WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);  in atombios_crtc_disable()
2160 		    i != radeon_crtc->crtc_id &&  in atombios_crtc_disable()
2161 		    radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {  in atombios_crtc_disable()
2169 	switch (radeon_crtc->pll_id) {  in atombios_crtc_disable()
2173 		atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,  in atombios_crtc_disable()
2182 			atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,  in atombios_crtc_disable()
2189 	radeon_crtc->pll_id = ATOM_PPLL_INVALID;  in atombios_crtc_disable()
2190 	radeon_crtc->adjusted_clock = 0;  in atombios_crtc_disable()
2191 	radeon_crtc->encoder = NULL;  in atombios_crtc_disable()
2192 	radeon_crtc->connector = NULL;  in atombios_crtc_disable()
2208 			       struct radeon_crtc *radeon_crtc)  in radeon_atombios_init_crtc()  argument
2213 		switch (radeon_crtc->crtc_id) {  in radeon_atombios_init_crtc()
2216 			radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2219 			radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2222 			radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2225 			radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2228 			radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2231 			radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
2235 		if (radeon_crtc->crtc_id == 1)  in radeon_atombios_init_crtc()
2236 			radeon_crtc->crtc_offset =  in radeon_atombios_init_crtc()
2239 			radeon_crtc->crtc_offset = 0;  in radeon_atombios_init_crtc()
2241 	radeon_crtc->pll_id = ATOM_PPLL_INVALID;  in radeon_atombios_init_crtc()
2242 	radeon_crtc->adjusted_clock = 0;  in radeon_atombios_init_crtc()
2243 	radeon_crtc->encoder = NULL;  in radeon_atombios_init_crtc()
2244 	radeon_crtc->connector = NULL;  in radeon_atombios_init_crtc()
2245 	drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);  in radeon_atombios_init_crtc()