557 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_update_vs_emph()  argument
560 	atombios_dig_transmitter_setup(dp_info->encoder,  in radeon_dp_update_vs_emph()
562 				       0, dp_info->train_set[0]); /* sets all lanes at once */  in radeon_dp_update_vs_emph()
565 	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,  in radeon_dp_update_vs_emph()
566 			  dp_info->train_set, dp_info->dp_lane_count);  in radeon_dp_update_vs_emph()
569 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)  in radeon_dp_set_tp()  argument
574 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {  in radeon_dp_set_tp()
586 		atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);  in radeon_dp_set_tp()
596 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,  in radeon_dp_set_tp()
597 					  dp_info->dp_clock, dp_info->enc_id, rtp);  in radeon_dp_set_tp()
601 	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);  in radeon_dp_set_tp()
604 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_link_train_init()  argument
606 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);  in radeon_dp_link_train_init()
611 	radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);  in radeon_dp_link_train_init()
614 	if (dp_info->dpcd[3] & 0x1)  in radeon_dp_link_train_init()
615 		drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_init()
618 		drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_init()
622 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);  in radeon_dp_link_train_init()
625 	tmp = dp_info->dp_lane_count;  in radeon_dp_link_train_init()
626 	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))  in radeon_dp_link_train_init()
628 	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);  in radeon_dp_link_train_init()
631 	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);  in radeon_dp_link_train_init()
632 	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);  in radeon_dp_link_train_init()
635 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)  in radeon_dp_link_train_init()
636 		atombios_dig_encoder_setup(dp_info->encoder,  in radeon_dp_link_train_init()
639 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,  in radeon_dp_link_train_init()
640 					  dp_info->dp_clock, dp_info->enc_id, 0);  in radeon_dp_link_train_init()
643 	drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_init()
650 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_link_train_finish()  argument
655 	drm_dp_dpcd_writeb(dp_info->aux,  in radeon_dp_link_train_finish()
660 	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)  in radeon_dp_link_train_finish()
661 		atombios_dig_encoder_setup(dp_info->encoder,  in radeon_dp_link_train_finish()
664 		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,  in radeon_dp_link_train_finish()
665 					  dp_info->dp_clock, dp_info->enc_id, 0);  in radeon_dp_link_train_finish()
670 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_link_train_cr()  argument
676 	radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);  in radeon_dp_link_train_cr()
677 	memset(dp_info->train_set, 0, 4);  in radeon_dp_link_train_cr()
678 	radeon_dp_update_vs_emph(dp_info);  in radeon_dp_link_train_cr()
684 	dp_info->tries = 0;  in radeon_dp_link_train_cr()
687 		drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);  in radeon_dp_link_train_cr()
689 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in radeon_dp_link_train_cr()
690 						 dp_info->link_status) <= 0) {  in radeon_dp_link_train_cr()
695 		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in radeon_dp_link_train_cr()
700 		for (i = 0; i < dp_info->dp_lane_count; i++) {  in radeon_dp_link_train_cr()
701 			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in radeon_dp_link_train_cr()
704 		if (i == dp_info->dp_lane_count) {  in radeon_dp_link_train_cr()
709 		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in radeon_dp_link_train_cr()
710 			++dp_info->tries;  in radeon_dp_link_train_cr()
711 			if (dp_info->tries == 5) {  in radeon_dp_link_train_cr()
716 			dp_info->tries = 0;  in radeon_dp_link_train_cr()
718 		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in radeon_dp_link_train_cr()
721 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);  in radeon_dp_link_train_cr()
723 		radeon_dp_update_vs_emph(dp_info);  in radeon_dp_link_train_cr()
730 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in radeon_dp_link_train_cr()
731 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>  in radeon_dp_link_train_cr()
737 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)  in radeon_dp_link_train_ce()  argument
741 	if (dp_info->tp3_supported)  in radeon_dp_link_train_ce()
742 		radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);  in radeon_dp_link_train_ce()
744 		radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);  in radeon_dp_link_train_ce()
747 	dp_info->tries = 0;  in radeon_dp_link_train_ce()
750 		drm_dp_link_train_channel_eq_delay(dp_info->dpcd);  in radeon_dp_link_train_ce()
752 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in radeon_dp_link_train_ce()
753 						 dp_info->link_status) <= 0) {  in radeon_dp_link_train_ce()
758 		if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in radeon_dp_link_train_ce()
764 		if (dp_info->tries > 5) {  in radeon_dp_link_train_ce()
770 		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);  in radeon_dp_link_train_ce()
772 		radeon_dp_update_vs_emph(dp_info);  in radeon_dp_link_train_ce()
773 		dp_info->tries++;  in radeon_dp_link_train_ce()
781 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in radeon_dp_link_train_ce()
782 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)  in radeon_dp_link_train_ce()
797 	struct radeon_dp_link_train_info dp_info;  in radeon_dp_link_train()  local
818 	dp_info.use_dpencoder = true;  in radeon_dp_link_train()
822 			dp_info.use_dpencoder = false;  in radeon_dp_link_train()
826 	dp_info.enc_id = 0;  in radeon_dp_link_train()
828 		dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;  in radeon_dp_link_train()
830 		dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;  in radeon_dp_link_train()
832 		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;  in radeon_dp_link_train()
834 		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;  in radeon_dp_link_train()
839 			dp_info.tp3_supported = true;  in radeon_dp_link_train()
841 			dp_info.tp3_supported = false;  in radeon_dp_link_train()
843 		dp_info.tp3_supported = false;  in radeon_dp_link_train()
846 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);  in radeon_dp_link_train()
847 	dp_info.rdev = rdev;  in radeon_dp_link_train()
848 	dp_info.encoder = encoder;  in radeon_dp_link_train()
849 	dp_info.connector = connector;  in radeon_dp_link_train()
850 	dp_info.dp_lane_count = dig_connector->dp_lane_count;  in radeon_dp_link_train()
851 	dp_info.dp_clock = dig_connector->dp_clock;  in radeon_dp_link_train()
852 	dp_info.aux = &radeon_connector->ddc_bus->aux;  in radeon_dp_link_train()
854 	if (radeon_dp_link_train_init(&dp_info))  in radeon_dp_link_train()
856 	if (radeon_dp_link_train_cr(&dp_info))  in radeon_dp_link_train()
858 	if (radeon_dp_link_train_ce(&dp_info))  in radeon_dp_link_train()
861 	if (radeon_dp_link_train_finish(&dp_info))  in radeon_dp_link_train()